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A Design Automation Tool for Integrated Nanophotonics based on Compact Modeling and Model Order Reduction

Award Information
Agency: Department of Defense
Branch: Office of the Secretary of Defense
Contract: FA9550-14-C-0031
Agency Tracking Number: O133-C05-1052
Amount: $149,989.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: OSD13-C05
Solicitation Number: 2013.3
Solicitation Year: 2013
Award Year: 2014
Award Start Date (Proposal Award Date): 2014-05-28
Award End Date (Contract End Date): 2014-11-30
Small Business Information
Huntsville, AL 35805-1926
United States
DUNS: 185169620
HUBZone Owned: No
Woman Owned: Yes
Socially and Economically Disadvantaged: No
Principal Investigator
 Yi Wang
 (256) 327-0678
Business Contact
 Deborah Phipps
Title: Contracts Manager
Phone: (256) 726-4884
Research Institution

Existing physics-based device simulation tools are prohibitively expensive computationally, and therefore ill-suited for parametric analysis and design optimization of photonic integrated circuits (PIC). The proposed effort aims to develop and demonstrate an innovative, easy-to-use simulation tool for accurate, fast circuit/system analysis of PICs. The salient aspects of the proposed solution are: (1) mathematically rigorous compact modeling and model order reduction (MOR) techniques bridge the gap between high-fidelity device simulation and existing EDA environment, and significantly accelerate the circuit/system simulation for large-scale PICs; (2) compact and reduced order models are automatically derived from first principle-based, high-fidelity device simulation to retain the analysis accuracy and predictive capabilities; and (3) a modular software framework to automate the entire simulation process and seamless integration to EDA tools. In Phase I, a data interface to photonic device simulation, a compact modeling module, a MOR engine encapsulating carefully chosen algorithms, and a ROM assembler for circuit/system simulation will be developed in an integrated environment. Feasibility will be demonstrated by case studies of DoD interest, in which a verification circuit will be selected and designed using the developed software. Its computational performance (e.g., accuracy, speed, reliability, and integrability to existing tools) will be assessed. The Phase II effort will focus on enhancing computational engine, optimizing software architecture, user-interface, and integration, and extensive validation and demonstration using fabricated circuits.

* Information listed above is at the time of submission. *

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