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Radiation Hard Monolithic SDRAM to Support DDR2 and DDR3 Architectures

Award Information
Agency: National Aeronautics and Space Administration
Branch: N/A
Contract: NNX14CJ44C
Agency Tracking Number: 120202
Amount: $748,194.00
Phase: Phase II
Program: STTR
Solicitation Topic Code: T15.01
Solicitation Number: N/A
Timeline
Solicitation Year: 2012
Award Year: 2014
Award Start Date (Proposal Award Date): 2014-09-08
Award End Date (Contract End Date): 2016-09-07
Small Business Information
10237 Flanders Court
San Diego, CA 92121-1526
United States
DUNS: 020817883
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Bert Vermeire
 Chief Technical Officer (CTO)
 (858) 332-0700
 bvermeire@spacemicro.com
Business Contact
 David Strobel
Title: Business Official
Phone: (858) 332-0700
Email: dstrobel@spacemicro.com
Research Institution
 Arizona State University
 David Strobel
 
660 South Mil Avenue, Suite 312
Tempe, AZ 85287
United States

 (858) 332-0700
 Domestic Nonprofit Research Organization
Abstract

Space Micro has developed the architecture for a radiation hardened memory subsystem that targets DDR3-and-beyond generations of DRAM. The architecture combines server platform error correction and memory buffer-on-board schemes with Space Micro proprietary techniques for radiation hardening and size, weight, and power reduction. During the NASA Phase I effort, Space Micro demonstrated two key elements of the architecture: (1) a scalable error correction coding (ECC) scheme that optimizes the robustness vs. efficiency vs. chip count tradespace, and (2) a Rad Hard By Design (RHBD) timing circuit for advanced DRAM fly-by routing. Space Micro has developed a Phase II plan for developing a server platform-like bridge chip that integrates ECC, interface logic, and timing circuitry into a high performance, low size, weight, and power (SWaP) memory subsystem suitable for next generation spacecraft computing.

* Information listed above is at the time of submission. *

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