High-Sample Rate Analog to Digital Converters for Reconfigurable Phased Array Applications

* PROPOSALS ACCEPTED: Phase I and DP2 (Direct to Phase II). Please see the 15.3 DoD Program Solicitation and the DARPA 15.3 Phase I Instructions for Phase I requirements and proposal instructions.*

TECHNOLOGY AREA(S): Electronics, Sensors

OBJECTIVE: Develop high-sample rate, low power, analog-to-digital converters (ADCs) for elemental digital phased array antennas. By the end of Phase II of the program, the ADCs should have a demonstrated effective number of bits (ENOB) > 6 bits, conversion rate of > 40 Giga samples per second (GS/s), analog bandwidth >20 GHz and power consumption < 500 mW.

DESCRIPTION: The ability to quickly and efficiently convert radio frequency (RF) signals to the digital domain where the underlying information can be processed using digital signal processing is a critical aspect of many DoD electronics systems. A specific example are phased array antenna systems, where high speed analog-to-digital converters (ADCs) enable the RF frequency band selection and RF beam steering to be performed using flexible and adaptive digital signal processing.

Recently, great advances have been made in high sample rate (>10 GS/s), yet energy efficient ADCs [1-3], dramatically improving the well-known Walden figure-of-merit (FOM). Yet, improvements in dynamic range, analog bandwidth and especially power consumption are needed for these converters. 

To meet the needs of the DoD, this solicitation seeks high-sample rate ADCs that can meet the specifications of an ENOB greater than 6 bits, conversion rate faster than 40 GS/s, analog bandwidth greater than 20 GHz and power consumption less than 500 mW by the end of Phase II of the program. Designs may use digitally-assisted or other methods to improve performance. Especially of interest are ADC implementations that have beneficial physics based scaling in advanced CMOS technology nodes of 32 nm and below.

PHASE I: Develop, analyze and sufficiently simulate an ADC architecture with a predicted performance of:

1. Power < 500 mW
2. ENOB > 6bits
3. Data Rate > 40 GS/s
4. Analog Bandwidth > 20 GHz
5. FOM < 200 fJ/conversion-step

Required Phase I deliverables will include:

1. A report detailing the ADC architecture, design and expected performance.

PHASE II: Use Phase I analysis to design, build, and successfully demonstrate the operation of a prototype ADC for Government evaluation with the following specifications:

1. Power < 500 mW
2. ENOB > 6bits
3. Data Rate > 40 GS/s
4. Analog Bandwidth > 20 GHz
5. FOM < 200 fJ/conversion-step

Required Phase II deliverables include:

1. Report containing design, simulation, layout files and test results from 2 ADC chips.
2. Delivery of 2 packaged ADC chips to the government.
3. Any necessary GDS or equivalent layout files to allow the Government to re-fabricate the design.
4. A datasheet containing all the information needed for the government to characterize the chip, use the chip in an application or incorporate the data converter design and layout into a larger integrated circuit.

PHASE III DUAL USE APPLICATIONS: In the emerging 5G standard for wireless handsets, phased arrays are expected to supply the spatial filtering needed to massively increase the number of handsets supported by a single base station. Digital phased arrays would further add to the flexibility and number of simultaneous users (handsets) but further increases in ADC sample rate and bandwidth are required for digital phased arrays to emerge at 5G.

Much like the Phase III commercial communications application, high-sample rate ADCs for DoD/Military applications are of great importance. Multiple-input multiple-output (MIMO) radio frequency systems are an effective method for in-theatre communications. These ADCs are a crucial component to breaking through the limitations of current MIMO systems to create MIMO systems supporting a greatly increased number of carriers and thus communications bandwidth.

In order to reach the goals of future communications systems, Phase III ADC metrics are as follows:

1. Power < 500 mW
2. ENOB > 6b
3. Sample > 80 GS/s
4. Analog Bandwidth > 40 GHz

KEYWORDS: ADC, A/D, analog-to-digital conversion, data converter, phased array