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Wafer-Level Electronic-Photonic Co-Packaging

Description:

TECHNOLOGY AREA(S): Electronics

OBJECTIVE: Develop flexible, low-cost packaging techniques for large-scale, integrated optoelectronic systems based on heterogeneously integrated photonic and electronic chips.

DESCRIPTION: Today, the military and commercial application spaces for silicon photonics are expanding very rapidly. The first wave of commercial products are aimed at the telecommunications and data communications spaces, but applications in sensing, analog data processing, coherent systems, laser ranging, and many other areas are rapidly emerging. A key innovation in recent years in the electronics industry has been the development of through-silicon vias and low-parasitic interposer technologies. These technologies open a path toward very inexpensive fabrication of electronic-photonic systems utilizing generic foundry CMOS and RF CMOS. The silicon photonic chips can be fabricated using trailing-edge technologies, while the electronics is built using commonly available generic processes, without any front-end modification.

At the same time, packaging of circuits involving coupling external light into passive components such as resonators, filters, waveguides, etc., as well as coupling external light into active devices such as modulators, face tremendous challenges due to unavailability of a standard fiber-chip packaging interface. Tremendous insertion losses resulting from traditional fiber-chip coupling strategies lead to establishment of a poor power budget, and therefore, pose a significant risk to photonic lightwave circuit (PLC) commercialization and to its large-scale utilization in diagnostics. Innovative fiber-to-chip packaging strategies, including but not limited to efficient grating couplers, inverse tapers, polymeric couplers, etc., are needed to put silicon photonics at the forefront of rapidly evolving markets. Of significant importance is also the challenges that have emerged for co-packaging of high performance lasers with silicon photonic circuits, and inexpensive fiber coupling of these chips. At the moment, the laser and fiber attach strategies that are inexpensive require substantial risk and are difficult to operate at high power, while the low-risk solutions provide very little optical power and are very expensive. Strategies that efficiently bring light from high performance lasers directly to the device's input are highly sought with easy attachment and detachment of semiconductor laser and detector arrays.

The technical areas to investigate include (1) new architecture designs for the integration of the photonic and electronic chip (including 3D or alternatives to 3D stacking approaches), new material composition and platforms, and new design for the optoelectronic chip package; (2) ultra-low parasitic bonding between foundry CMOS or RF-CMOS and silicon photonic components, with high interconnect density, low cost, and high yield; (3) wafer-scale (wafer-wafer or die-wafer) bonding technology; (4) electronic-photonic co-design environment suitable for system integration at a large scale, including very complex electronic-photonic systems; (5) low-cost packaging strategy for this bonded chip that provides the capability of adding efficient solid state optical sources to the platform, ideally based on off-the-shelf technology; (6) low-cost and efficient pigtailing strategy for the bonded chip with focus on reducing the insertion loss; (7) flexible, low-cost strategies to create a package that can handle many RF inputs and outputs, many optical IO's, and many DC IO's; and (8) military specific strategies, such as hybrid microwave-photonic packaging platform. All approaches taken should keep mixed technologies in mind and leverage off-the-shelf CMOS and existing foundry-based silicon photonic processes and focus on low cost, automated processes which will enable high-speed optoelectronic chips. The effort should identify at least one military transition partner with a need for a technology demonstrator in this technology, and develop the design of this demonstrator.

PHASE I: Develop and demonstrate plausibility of an approach that meets the above metrics, for building and packaging bonded electronic-photonic systems on-chip. Develop a test chip design with a large number of interconnections between photonic and electronic chip in order to test performance in Phase II. Develop and demonstrate efficient fiber-to-chip coupling strategies.

PHASE II: Fabricate the circuit developed in Phase I, and test it to validate the tool flow developed in Phase I and work with the military transition partner. Establish performance and feasibility of the platform. Demonstrate fiber pigtailing and laser attachment. Experimentally validate against the ability to survive military environmental specifications.

PHASE III DUAL USE APPLICATIONS: Military applications include RF signal processing, radar, imaging systems, high speed communications, and onboard sensor networks.
Commercial applications: High performance computing, telecommunications, networking, data processing.

REFERENCES:

    • L. Zimmermann, P. G. Battista, T. Tekin Tolga, et al., “Packaging and Assembly for Integrated Photonics-A Review of the ePIXpack Photonics Packaging Platform,” IEEE J. Sel. Quant., 17, 645-651, (2011).

 

    • “CMOS integrated optical receivers for on-chip interconnects,” S. Assefa, C. Schow, F. Xia, W. M. J. Green, A. Rylyakov, and Y. Vlasov.

 

    • 3D silicon integration. Knickerbocker et al., 2008.

 

    • Impact of 3d design choices on manufacturing cost. Velenis, D. et al., 2009.

 

    • R. Halir, P. Cheben, S. Janz, D-X. Xu, I. Molina-Fernandez, and J.G. Wanguemert-Perez, "Waveguide grating coupler with subwavelength microstructures," Opt. Lett. 34 (9), 1408 (2009).

 

  • A. H. Pham, M. Chen, and K. Aihara, LCP for Microwave Packages and Modules, Cambridge University Press, Cambridge. 2012.

KEYWORDS: Optoelectronic packaging, large scale integrated optics systems, monolithic integration, hybrid integrated-circuit packaging, photonic integration, heterogeneous integration, fiber optic coupling, silicon-on-insulator, SOI, 3D integration, IC packaging, photonics packaging, mixed technology, silicon photonics, foundry, low cost, automated processes, packaging, RF photonics, microwave photonics

  • TPOC-1: Gernot Pomrenke
  • Phone: 703-696-8426
  • Email: gernot.pomrenke@us.af.mil
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