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Innovative Mitigation of Radiation Effects in Advanced Technology Nodes


TECHNOLOGY AREA(S): Electronics, Space Platforms

OBJECTIVE: Develop generic or automated radiation hardening tools software and / or hardware tools to advance the state-of-the-art of Rad Hard by Design (RHBD) techniques in advanced technology nodes.

DESCRIPTION: There is significant value in getting data as early as possible on the radiation response of new and advanced technologies nodes. Frequently, however, the “non-standard” structures required to support radiation response are not present in standard test chip patterns or scribe-line electrical test structures. Development of generic radiation effects characterization pcm test are needed to afford an early look at the detailed radiation response of the technology, enabling first-pass success “harden-by design” approaches for advanced technology nodes (features <90nm for RFCMOS, SiGe, and Heterogeneous Bipolar technology (HBT) and <45nm for digital CMOS). There is also a critical need for automated radiation hardening tools to advance the state-of-the-art Rad Hard by Design (RHBD) techniques in advanced technology nodes. Development of such tools will result in significant savings in the development of advanced radiation hardened circuits for critical DoD applications.

PHASE I: For generic characterization tools that will enable early radiation response: Demonstrate an initial evaluation of process and device sensitivities (using foundry electrical simulation models) to enable early access of radiation response. The outcome of the Phase I would include 1) identification of a specific list of the electrical structures and their geometries, and 2) a specific list of what electrical parameters (vs radiation exposure and bias) to be characterized in a Phase II effort. For the development of automated software tool that will advance the radiation by design (RHBD) techniques, the Phase I should focus on developing models of charge generation, charge collection, and circuit response using existing data from literature and computer models (ex. TCAD, LSPICE). The result of this Phase I should be a description of simulation or modeling results that will advance RHBD techniques.

PHASE II: For generic characterization tool that will enable early radiation response: Demonstrate the technology to develop a generic characterization process for early access of radiation response of sample test structures. The technology demonstration in Phase II will include 1) a gds layout file of all the associated test devices and circuits, 2) build test silicon, 3) generate accompanying documentation for those structures and circuits, and 4) design and execute a test plan of what parameters (vs radiation exposure and bias conditions). For the development of automated codes that will advance RHBD techniques, the Phase II effort should develop 1) device and or circuit models with RHBD layout constraints to mitigate single event effects and 2) validate the radiation charge generation, charge collection, and circuit response models developed in Phase I. The Phase II should also include preliminary design, fabrication, and radiation testing of simple test structures needed to validate the radiation induced SEE response models and RHBD mitigation schemes developed in Phase I and II. The RHBD mitigation schemes should include either a memory, logic, I/O, Phase Lock Loops, Delay Lock Loops, or analogy mixed signal circuits. Industry and government partners for Phase III must be identified along with demonstration of their support. A roadmap that takes the program through Phase III must be part of the final delivery for Phase II.

PHASE III DUAL USE APPLICATIONS: For generic characterization tool that will enable early radiation response, the final outcome is to provide electric and layout parameters necessary to support design of these products to enable the space and defense community to execute first-pass-success radiation-tolerant or radiation-hardened designs. This Phase III should include initial silicon fabrication, and an exhaustive electrical characterization (vs radiation exposure) of the silicon. Parametric shifts as a function of radiation exposure and bias should be characterized, and electrical design parameters shall be made available to the design community. For development of software codes to advance RHBD, the Phase III should include development of macros for mitigation of radiation effects in common electronic circuits and development of software and / or hardware architecture. This Phase should also automate the implementation of the circuit macros in software and / or hardware architecture developed in Phase II and makes the technology available to USERS developing RHBD circuit designs.


    • Kai, K., et al. "Channel dopant profile and Leff extraction of deep submicron MOSFETs by Inverse Modeling." Simulation of Semiconductor Processes and Devices, 1996. SISPAD 96. 1996 International Conference on IEEE, 1996.


    • Groeseneken, G., Maes, H. E., Beltran, N., & De Keersmaecker, R. F. (1984). A reliable approach to charge-pumping measurements in MOS transistors. Electron Devices, IEEE transactions on, 31(1), 42-53.


    • C. Jan et al, IEDM 2012 Tech Dig. pp 44-47, 2012


  • A. T. Kelly, et al. “Kernel-Based Circuit Partition Approach to Mitigate Combinational Logic Soft Errors”, IEEE Trans. On Nuclear Science, vol 61, no.6, pp.3274-3281, Dec. 2014.

KEYWORDS: Materials/Processes, Nano-technology, Nuclear Technologies, Single-Event Effect, Total Ionization Dose, Radiation Hardened Microelectronics

  • TPOC-1: Bruce Wilson
  • Phone: 703-767-3667
  • Email:
  • TPOC-2: Pauline Paki
  • Phone: 703-767-2886
  • Email:
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