Award Data

During Phase I and a first Phase II, Welkin Sciences developed the Channel Realization Generator (CReG) algorithm, an enhanced functional replacement for the ACIRF code intended to be embedded into software link simulations and HWIL fading channel simulators. The proposed second Phase II effort will refine the CReG documentation and its software and firmware implementations. Many in the strategic ...

The Defense Threat Reduction Agency (DTRA) recognizes the need for low-power high-bandwidth radiation-hard optical interconnects to process more data more quickly and to replace electronic data.Our companys core development in optical communications with semiconductor materials is a unique fit for DTRAs low-power consumption high-bandwidth radiation-hard intra-chip communication components for sat ...

In this proposed Phase II program we will build on the successful Phase I program where we for the first time implemented engineered epitaxial layers based on nanostructure technology that were used to harden commercial silicon devices against radiation by minimizing collected photocurrents (electron-hole pairs) via recombination centers where we demonstrated that improved radiation hardness could ...

Weidlinger Associates Inc. proposes to develop effective technology for simulating explosive detonations within civil buildings where the propagation of airblast and failure of weak internal walls are strongly coupled. We will conduct a field test program designed to complement other internal detonation testing efforts such as DTRA''s Distinct Cobra, expanding the available database. We will perfo ...

In Phase I of this effort we analyzed the structural response of a BLU 109 during typical penetration events. Based on these finite element results, we proposed and demsonstrated a simple robust concept for a passive penetrator sensor that identifies the material being penetrated and also correlates strongly with its underground trajectory. Such a sensor would obviously provide valuable informatio ...

Orora Design Technologies proposes to develop electronic design automation (EDA) tools employing minimally invasive circuit design-based methods to mitigate single event effects (SEEs) for next generation Ultra-DSM CMOS (

As technology feature sizes decrease, single event upset (SEU), digital single event transient (DSET), and multiple bit upset (MBU) effects dominate the radiation response of microcircuits. Recent test circuits and test methods have quantified the pulse widths of DSETs generated from heavy-ion strikes on critical microcircuit nodes. These pulse widths have proven to be much larger than previousl ...