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The Award database is continually updated throughout the year. As a result, data for FY20 is not expected to be complete until September, 2021.
SBC: SILICON TECHNOLOGIES, INC. Topic: DTRA143008
The DoD faces mounting costs for integrated circuits built with advanced technology. Our proposal addresses mixed-signal ASIC design costs and fabrication costs, notably photomask costs and photolithography costs. The ADONIS 1D design methodology has been demonstrated at technologies ranging from 130nm to 16nm. In Phase I of the program, we used ADONIS to design a reference circuit a high-speed c ...SBIR Phase II 2017 Department of DefenseDefense Threat Reduction Agency
The Characterization and Mitigation of Single Event Effects in Ultra-Deep Submicron (< 90nm) MicroelectronicsSBC: Orora Design Technologies, Inc. Topic: DTRA07005
Orora Design Technologies proposes to develop electronic design automation (EDA) tools employing minimally invasive circuit design-based methods to mitigate single event effects (SEEs) for next generation Ultra-DSM CMOS (SBIR Phase II 2008 Department of DefenseDefense Threat Reduction Agency
SBC: Thornton Tomasetti, Inc. Topic: DTRA07011
In Phase I of this effort we analyzed the structural response of a BLU 109 during typical penetration events. Based on these finite element results, we proposed and demsonstrated a simple robust concept for a passive penetrator sensor that identifies the material being penetrated and also correlates strongly with its underground trajectory. Such a sensor would obviously provide valuable informatio ...SBIR Phase II 2008 Department of DefenseDefense Threat Reduction Agency