Award Data

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The Award database is continually updated throughout the year. As a result, data for FY19 is not expected to be complete until June, 2020.

  1. Memory Instrumentation and Performance Simulation (MIPS)

    SBC: ATC-NY, Inc.            Topic: DTRA172003

    Next-generation high-performance computing (HPC) hardware, such as the Intel Xeon Phi Knights Landing Many-Integrated-Core processor, provide new deep memory architectures that offer the promise of increased performance. The challenge in taking full advantage of this architecture is selecting which data structures will be placed in the high-bandwidth memory. Optimizing data structure placement in ...

    SBIR Phase I 2018 Department of DefenseDefense Threat Reduction Agency
  2. Low-Cost Sensing Array for Infrasound

    SBC: CREARE LLC            Topic: DTRA172001

    Infrasound and seismic measurements are used by DTRA and the DoD for nuclear test monitoring, terrorist blast forensics, battle damage assessment, and environmental monitoring. However, these long wavelength physical signals are typically recorded through single-point sensors or sparse low density arrays. As a result, the critical signals of interest are often corrupted or masked by noise or inter ...

    SBIR Phase I 2018 Department of DefenseDefense Threat Reduction Agency
  3. Additive Manufacturing of All Solid-State Batteries with Novel Electrode Architectures

    SBC: Storagenergy Technologies, Inc.            Topic: DTRA172005

    Supercapacitors have attracted considerable recent attentions due to their high-power density, and long cycle life. Unfortunately, the energy density of supercapacitors is too low to meet these applications requiring an energy supply for longer periods (hours or days). Storagenergy Technologies Inc. proposes to develop a superior all solid-state battery (ASSB) fabricated by additive manufacturing ...

    SBIR Phase I 2018 Department of DefenseDefense Threat Reduction Agency
  4. A Robust, Machine Independent, Software Toolkit for Topology Aware Process Mapping on Distributed Memory HPC Architectures

    SBC: Continuum Dynamics Inc            Topic: DTRA172002

    A significant performance gap exists between the theoretical number of Floating Point Operations (FLOPS) that a HPC machine is capable of sustaining and the number of FLOPS realized by real-world HPC applications. One of the principle reasons for this gap is the parasitic work that computational processes must do to communicate with one another. It has been shown that this communication work can b ...

    SBIR Phase I 2018 Department of DefenseDefense Threat Reduction Agency
  5. High Fidelity Modeling of Building Collapse with Realistic Visualization of Resulting Damage and Debris

    SBC: Thornton Tomasetti, Inc.            Topic: DTRA082005

    The proposed Phase II effort investigates innovative finite element formulations, alternative structural modeling procedures and modern parallel computational strategies to improve the computational performance of high fidelity simulation software for modeling the progressive collapse behavior of blast damaged buildings. Its goal is to reduce the time required to compute and visualize high fideli ...

    SBIR Phase II 2010 Department of DefenseDefense Threat Reduction Agency
  6. Next Generation Blast Simulation

    SBC: Reaction Engineering International            Topic: DTRA092015

    With the current state of world events, the threat of explosives used against high-value targets is more pronounced than ever before. As a result, simulation of blast events and their effects on structures has become an increasingly vital capability. Current blast simulations on Central Processing Units (CPU) resources require a significant amount of computational time, limiting their overall valu ...

    SBIR Phase I 2010 Department of DefenseDefense Threat Reduction Agency
  7. Continuous Wave Compressive Sensing Terahertz Spectrometer for Low Vapor Pressure Standoff Detection

    SBC: Princeton Nanotechnology Systems LLC            Topic: DTRA092005

    PNTS proposes to develop a truly novel implementation of eye-safe terahertz (THz) spectroscopy that is unprecedented in the standoff detection regime for accuracy, low cost, and portability. PNTS has teamed with SC&A, Inc., and researchers from the University of Memphis to create a world class team of research and development personnel. We are proposing a continuous wave terahertz (THz-CW) spect ...

    SBIR Phase I 2010 Department of DefenseDefense Threat Reduction Agency
  8. Standoff Sensing for Low Volatility Chemicals Using Terahertz Radiation-Enhanced-Emission-of-Fluorescence

    SBC: Zomega Terahertz Corporation            Topic: DTRA092005

    We propose a new active optical method to measure time-domain waveform of THz pulse in the vicinity of the target in an omni-directional manner. This method utilizes the THz radiation-enhanced-emission-of-fluorescence from laser-induced air plasma to detect the THz field, which enables the standoff sensing for low volatility chemicals using THz spectroscopy. We have demonstrated its capability of ...

    SBIR Phase I 2010 Department of DefenseDefense Threat Reduction Agency
  9. Novel Methods to Measure Penetrator Dynamics in Multi-Layer Geometries

    SBC: Thornton Tomasetti, Inc.            Topic: DTRA07011

    In Phase I of this effort we analyzed the structural response of a BLU 109 during typical penetration events. Based on these finite element results, we proposed and demsonstrated a simple robust concept for a passive penetrator sensor that identifies the material being penetrated and also correlates strongly with its underground trajectory. Such a sensor would obviously provide valuable informatio ...

    SBIR Phase II 2008 Department of DefenseDefense Threat Reduction Agency
  10. The Characterization and Mitigation of Single Event Effects in Ultra-Deep Submicron (< 90nm) Microelectronics

    SBC: Orora Design Technologies, Inc.            Topic: DTRA07005

    Orora Design Technologies proposes to develop electronic design automation (EDA) tools employing minimally invasive circuit design-based methods to mitigate single event effects (SEEs) for next generation Ultra-DSM CMOS (

    SBIR Phase II 2008 Department of DefenseDefense Threat Reduction Agency
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