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Award Data
The Award database is continually updated throughout the year. As a result, data for FY24 is not expected to be complete until March, 2025.
Download all SBIR.gov award data either with award abstracts (290MB)
or without award abstracts (65MB).
A data dictionary and additional information is located on the Data Resource Page. Files are refreshed monthly.
The SBIR.gov award data files now contain the required fields to calculate award timeliness for individual awards or for an agency or branch. Additional information on calculating award timeliness is available on the Data Resource Page.
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Low Voltage Radiation Hardened Optoelectronics for Optical Interconnects
SBC: Quanttera LLC Topic: DTRA152001The Defense Threat Reduction Agency (DTRA) recognizes the need for low-power high-bandwidth radiation-hard optical interconnects to process more data more quickly and to replace electronic data.Our companys core development in optical communications with semiconductor materials is a unique fit for DTRAs low-power consumption high-bandwidth radiation-hard intra-chip communication components for sat ...
SBIR Phase II 2018 Department of DefenseDefense Threat Reduction Agency -
Hierarchical, Layout-Aware, Radiation Effects Tools Vertically Integrated into an EDA Design Flow for Rad-Hard by Design
SBC: RELIABLE MICROSYSTEMS LLC Topic: DTRA16A003The goal of this workis to establish a radiation-aware capability in a commercial EDA design flow that will enable first-pass success in radiation resiliency for DoD ASIC designs in much the same way that existing EDA design suites ensure first pass functionality and performance success of complex ASICs destined for commercial applications.Such an integrated capability does not presently exist.The ...
STTR Phase II 2018 Department of DefenseDefense Threat Reduction Agency -
The Characterization and Mitigation of Single Event Effects in Ultra-Deep Submicron (< 90nm) Microelectronics
SBC: Orora Design Technologies, Inc. Topic: DTRA07005Orora Design Technologies proposes to develop electronic design automation (EDA) tools employing minimally invasive circuit design-based methods to mitigate single event effects (SEEs) for next generation Ultra-DSM CMOS (
SBIR Phase II 2008 Department of DefenseDefense Threat Reduction Agency
