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The Award database is continually updated throughout the year. As a result, data for FY24 is not expected to be complete until March, 2025.

Download all SBIR.gov award data either with award abstracts (290MB) or without award abstracts (65MB). A data dictionary and additional information is located on the Data Resource Page. Files are refreshed monthly.

The SBIR.gov award data files now contain the required fields to calculate award timeliness for individual awards or for an agency or branch. Additional information on calculating award timeliness is available on the Data Resource Page.

  1. XpressRules-PM: Commercial Implementation of PM/NGAC

    SBC: XpressRules LLC            Topic: NA

    New Generation Access Control (NGAC)—because of its “neutrality by design”—represents the most effective and scalable approach for deploying “smart” access control and consent solutions in large dynamic scenarios. NGAC however presents with its own problems: (1) it has miniscule recognition and uptake in the workplace, (2) it is unusable by non-technical policy officers and (3) its doc ...

    SBIR Phase II 2018 Department of CommerceNational Institute of Standards and Technology
  2. High Temperature High Resolution in-situ Differential Pressure Sensor

    SBC: Innoveering, LLC            Topic: NA

    Chemical manufacturers require high accuracy/high sensitivity pressure sensors to efficiently monitor the various manufacturing systems and processes in the chemical plant, to ensure any changes proceed in a safe and reliable manner, adhering to expected standards and practices. NIST also has a need for highly accurate pressure measurements, especially determining the thermo-physical properties of ...

    SBIR Phase II 2017 Department of CommerceNational Institute of Standards and Technology
  3. Lithography Cost Reduction for Rad Hard Integrated Circuits

    SBC: SILICON TECHNOLOGIES, INC.            Topic: DTRA143008

    The DoD faces mounting costs for integrated circuits built with advanced technology. Our proposal addresses mixed-signal ASIC design costs and fabrication costs, notably photomask costs and photolithography costs. The ADONIS 1D design methodology has been demonstrated at technologies ranging from 130nm to 16nm. In Phase I of the program, we used ADONIS to design a reference circuit a high-speed c ...

    SBIR Phase II 2017 Department of DefenseDefense Threat Reduction Agency
  4. Novel Methods to Measure Penetrator Dynamics in Multi-Layer Geometries

    SBC: Thornton Tomasetti, Inc.            Topic: DTRA07011

    In Phase I of this effort we analyzed the structural response of a BLU 109 during typical penetration events. Based on these finite element results, we proposed and demsonstrated a simple robust concept for a passive penetrator sensor that identifies the material being penetrated and also correlates strongly with its underground trajectory. Such a sensor would obviously provide valuable informatio ...

    SBIR Phase II 2008 Department of DefenseDefense Threat Reduction Agency
  5. The Characterization and Mitigation of Single Event Effects in Ultra-Deep Submicron (< 90nm) Microelectronics

    SBC: Orora Design Technologies, Inc.            Topic: DTRA07005

    Orora Design Technologies proposes to develop electronic design automation (EDA) tools employing minimally invasive circuit design-based methods to mitigate single event effects (SEEs) for next generation Ultra-DSM CMOS (

    SBIR Phase II 2008 Department of DefenseDefense Threat Reduction Agency
  6. The development of a Single-Event upset immune, re-programmable and non-volatile field programmable gate array (r-NV-FPGA)

    SBC: STRUCTURED MATERIALS INDUSTRIES, INC.            Topic: MDA03056

    Radiation tolerant Field Programmable Gate Arrays (FPGA’s) have gained wide and rapid acceptance by military and aerospace equipment suppliers; however, there are presently a limited number of chip-sets available for production and they are limited to one time programming; hence if program changes are subsequently required a backup or chip replacement is required. The lack of FPGA alternatives ...

    SBIR Phase II 2005 Department of DefenseDefense Threat Reduction Agency
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