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The Award database is continually updated throughout the year. As a result, data for FY24 is not expected to be complete until March, 2025.

Download all SBIR.gov award data either with award abstracts (290MB) or without award abstracts (65MB). A data dictionary and additional information is located on the Data Resource Page. Files are refreshed monthly.

The SBIR.gov award data files now contain the required fields to calculate award timeliness for individual awards or for an agency or branch. Additional information on calculating award timeliness is available on the Data Resource Page.

  1. Real-Time Frequency-Selective Fading Channel Realization Generator

    SBC: WELKIN SCIENCES, LLC            Topic: DTRA122020

    During Phase I and a first Phase II, Welkin Sciences developed the Channel Realization Generator (CReG) algorithm, an enhanced functional replacement for the ACIRF code intended to be embedded into software link simulations and HWIL fading channel simulators. The proposed second Phase II effort will refine the CReG documentation and its software and firmware implementations. Many in the strategic ...

    SBIR Phase II 2018 Department of DefenseDefense Threat Reduction Agency
  2. Hardware-in-the-Loop Scintillation Simulator for MILSATCOM links in a Nuclear Disturbed Communication Environment

    SBC: WELKIN SCIENCES, LLC            Topic: DTRA172006

    In response to SBIR Topic DTRA172-006, Welkin Sciences proposes to design and build a new all-digital fading channel simulator to be called CoLTSAD. This new simulator design will be the latest addition to our family of Configurable Link Test Sets (CoLTS). It will be capable of emulating the full range of MIL-STD-3053 scintillating channel conditions for all SATCOM frequency bands up to Ka-band. C ...

    SBIR Phase I 2018 Department of DefenseDefense Threat Reduction Agency
  3. Memory Instrumentation and Performance Simulation (MIPS)

    SBC: ATC-NY INC            Topic: DTRA172003

    Next-generation high-performance computing (HPC) hardware, such as the Intel Xeon Phi Knights Landing Many-Integrated-Core processor, provide new deep memory architectures that offer the promise of increased performance. The challenge in taking full advantage of this architecture is selecting which data structures will be placed in the high-bandwidth memory. Optimizing data structure placement in ...

    SBIR Phase I 2018 Department of DefenseDefense Threat Reduction Agency
  4. Low-Cost Sensing Array for Infrasound

    SBC: CREARE LLC            Topic: DTRA172001

    Infrasound and seismic measurements are used by DTRA and the DoD for nuclear test monitoring, terrorist blast forensics, battle damage assessment, and environmental monitoring. However, these long wavelength physical signals are typically recorded through single-point sensors or sparse low density arrays. As a result, the critical signals of interest are often corrupted or masked by noise or inter ...

    SBIR Phase I 2018 Department of DefenseDefense Threat Reduction Agency
  5. Low Cost Large N Acoustic Array

    SBC: TDA RESEARCH, INC.            Topic: DTRA172001

    TDA Research Inc. (TDA) proposes to adapt off the shelf hardware and combine it with acoustic analysis techniques to develop an inexpensive, efficient, and scalable large number array of low cost acoustic sensors. Low frequency acoustic sensing detects a wide array of natural and manmade events including weather tracking, avalanche monitoring, explosion analysis, and nuclear test monitoring. By us ...

    SBIR Phase I 2018 Department of DefenseDefense Threat Reduction Agency
  6. Additive Manufacturing of All Solid-State Batteries with Novel Electrode Architectures

    SBC: STORAGENERGY TECHNOLOGIES INC            Topic: DTRA172005

    Supercapacitors have attracted considerable recent attentions due to their high-power density, and long cycle life. Unfortunately, the energy density of supercapacitors is too low to meet these applications requiring an energy supply for longer periods (hours or days). Storagenergy Technologies Inc. proposes to develop a superior all solid-state battery (ASSB) fabricated by additive manufacturing ...

    SBIR Phase I 2018 Department of DefenseDefense Threat Reduction Agency
  7. High Performance Computing (HPC) Tools for Topology Aware Mapping of Inter-node communication

    SBC: COMBUSTION RESEARCH & FLOW TECHNOLOGY INC            Topic: DTRA172002

    This proposal describes the development of a generalized toolkit that enables improved and automated mapping of partitioned subdomains onto available distributed compute nodes for applications operating within pure-MPI or hybrid-MPI parallel runtime environments. This toolkit may be invoked either as an independent pre-processing step or as a dynamic library, improving an applications real-time do ...

    SBIR Phase I 2018 Department of DefenseDefense Threat Reduction Agency
  8. A Robust, Machine Independent, Software Toolkit for Topology Aware Process Mapping on Distributed Memory HPC Architectures

    SBC: CONTINUUM DYNAMICS INC            Topic: DTRA172002

    A significant performance gap exists between the theoretical number of Floating Point Operations (FLOPS) that a HPC machine is capable of sustaining and the number of FLOPS realized by real-world HPC applications. One of the principle reasons for this gap is the parasitic work that computational processes must do to communicate with one another. It has been shown that this communication work can b ...

    SBIR Phase I 2018 Department of DefenseDefense Threat Reduction Agency
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