Award Data

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The Award database is continually updated throughout the year. As a result, data for FY19 is not expected to be complete until June, 2020.

  1. Memory Instrumentation and Performance Simulation (MIPS)

    SBC: ATC-NY, Inc.            Topic: DTRA172003

    Next-generation high-performance computing (HPC) hardware, such as the Intel Xeon Phi Knights Landing Many-Integrated-Core processor, provide new deep memory architectures that offer the promise of increased performance. The challenge in taking full advantage of this architecture is selecting which data structures will be placed in the high-bandwidth memory. Optimizing data structure placement in ...

    SBIR Phase I 2018 Department of DefenseDefense Threat Reduction Agency
  2. Low-Cost Sensing Array for Infrasound

    SBC: CREARE LLC            Topic: DTRA172001

    Infrasound and seismic measurements are used by DTRA and the DoD for nuclear test monitoring, terrorist blast forensics, battle damage assessment, and environmental monitoring. However, these long wavelength physical signals are typically recorded through single-point sensors or sparse low density arrays. As a result, the critical signals of interest are often corrupted or masked by noise or inter ...

    SBIR Phase I 2018 Department of DefenseDefense Threat Reduction Agency
  3. Additive Manufacturing of All Solid-State Batteries with Novel Electrode Architectures

    SBC: Storagenergy Technologies, Inc.            Topic: DTRA172005

    Supercapacitors have attracted considerable recent attentions due to their high-power density, and long cycle life. Unfortunately, the energy density of supercapacitors is too low to meet these applications requiring an energy supply for longer periods (hours or days). Storagenergy Technologies Inc. proposes to develop a superior all solid-state battery (ASSB) fabricated by additive manufacturing ...

    SBIR Phase I 2018 Department of DefenseDefense Threat Reduction Agency
  4. A Robust, Machine Independent, Software Toolkit for Topology Aware Process Mapping on Distributed Memory HPC Architectures

    SBC: Continuum Dynamics Inc            Topic: DTRA172002

    A significant performance gap exists between the theoretical number of Floating Point Operations (FLOPS) that a HPC machine is capable of sustaining and the number of FLOPS realized by real-world HPC applications. One of the principle reasons for this gap is the parasitic work that computational processes must do to communicate with one another. It has been shown that this communication work can b ...

    SBIR Phase I 2018 Department of DefenseDefense Threat Reduction Agency
  5. Hybrid Reactive Materials for Thermobaric Weapons

    SBC: REACTIVE METALS, INC.            Topic: DTRA06010

    It is proposed to produce and evaluate hybrid powders containing highly reactive filler coated by or embedded into a matrix of readily boiling, combustible binder. The binder material, such as paraffin wax and Viton-like rubber, are expected to ignite and burn within the expanding fireball while the reactive filler remains at the relatively low temperature at which the binder boils, and thus rema ...

    SBIR Phase II 2007 Department of DefenseDefense Threat Reduction Agency
  6. New Methods for Progressive Collapse Testing and Simulation

    SBC: Thornton Tomasetti, Inc.            Topic: DTRA06003

    The potential for progressive collapse of buildings damaged by terrorist blasts represents a significant risk to building occupants. There is a need for software tools that assess the potential for progressive collapse of above ground structures. These tools should run quickly and accurately predict the collapsed region of a damaged structure. These tools would be of great value to security pla ...

    SBIR Phase II 2007 Department of DefenseDefense Threat Reduction Agency
  7. The Characterization and Mitigation of Single Event Effects in Ultra-Deep Submicron (< 90nm) Microelectronics

    SBC: Orora Design Technologies, Inc.            Topic: DTRA07005

    Orora Design Technologies proposes the development of minimally invasive circuit design-based methods to mitigate single event effects (SEEs) in next generation Ultra-DSM CMOS (

    SBIR Phase I 2007 Department of DefenseDefense Threat Reduction Agency
  8. Novel Methods to Measure Penetrator Dynamics in Multi-Layer Geometries

    SBC: Thornton Tomasetti, Inc.            Topic: DTRA07011

    This proposal describes an approach to meeting DTRA’s goals of improving sensor technology for penetrating weapons. Weidlinger Associates Inc. (WAI) has significant experience in the design and use of ultrasound technologies for a broad range of end-use applications. WAI is also familiar with the terradynamic issues related to penetrators and the targeting aspects through its work in Hard Targ ...

    SBIR Phase I 2007 Department of DefenseDefense Threat Reduction Agency
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