Award Data

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The Award database is continually updated throughout the year. As a result, data for FY19 is not expected to be complete until June, 2020.

  1. Memory Instrumentation and Performance Simulation (MIPS)

    SBC: ATC-NY, Inc.            Topic: DTRA172003

    Next-generation high-performance computing (HPC) hardware, such as the Intel Xeon Phi Knights Landing Many-Integrated-Core processor, provide new deep memory architectures that offer the promise of increased performance. The challenge in taking full advantage of this architecture is selecting which data structures will be placed in the high-bandwidth memory. Optimizing data structure placement in ...

    SBIR Phase I 2018 Department of DefenseDefense Threat Reduction Agency
  2. A Robust, Machine Independent, Software Toolkit for Topology Aware Process Mapping on Distributed Memory HPC Architectures

    SBC: Continuum Dynamics Inc            Topic: DTRA172002

    A significant performance gap exists between the theoretical number of Floating Point Operations (FLOPS) that a HPC machine is capable of sustaining and the number of FLOPS realized by real-world HPC applications. One of the principle reasons for this gap is the parasitic work that computational processes must do to communicate with one another. It has been shown that this communication work can b ...

    SBIR Phase I 2018 Department of DefenseDefense Threat Reduction Agency
  3. Novel Methods to Measure Penetrator Dynamics in Multi-Layer Geometries

    SBC: Thornton Tomasetti, Inc.            Topic: DTRA07011

    In Phase I of this effort we analyzed the structural response of a BLU 109 during typical penetration events. Based on these finite element results, we proposed and demsonstrated a simple robust concept for a passive penetrator sensor that identifies the material being penetrated and also correlates strongly with its underground trajectory. Such a sensor would obviously provide valuable informatio ...

    SBIR Phase II 2008 Department of DefenseDefense Threat Reduction Agency
  4. The Characterization and Mitigation of Single Event Effects in Ultra-Deep Submicron (< 90nm) Microelectronics

    SBC: Orora Design Technologies, Inc.            Topic: DTRA07005

    Orora Design Technologies proposes to develop electronic design automation (EDA) tools employing minimally invasive circuit design-based methods to mitigate single event effects (SEEs) for next generation Ultra-DSM CMOS (

    SBIR Phase II 2008 Department of DefenseDefense Threat Reduction Agency
  5. Agent Defeat using a DWA Accelerator

    SBC: Brookhaven Technology Group, Inc.            Topic: DTRA08008

    A new type of compact induction accelerator currently under development at the Lawrence Livermore National Laboratory (LLNL) promises to increase the average accelerating gradient by at least an order of magnitude over that of existing induction machines. The machine is based on the use of high gradient vacuum insulators and advanced dielectric materials and switches. The system, called the Diel ...

    SBIR Phase I 2008 Department of DefenseDefense Threat Reduction Agency
  6. Engineering Models for Damage to Structural Components Subjected to Internal Blast Loading

    SBC: Thornton Tomasetti, Inc.            Topic: DTRA08006

    Predicting the response of building components to internal detonations is more complex than the corresponding task for external loads because of the more complex loading waveforms which include multiple reflections in the shock phase followed by a long duration pseudostatic loading that depends upon room venting. Add the possibility of additional impulsive loading from primary debris. We propose t ...

    SBIR Phase I 2008 Department of DefenseDefense Threat Reduction Agency
  7. Reactive Coating Materials as Lethality Enhancers

    SBC: STRUCTURED MATERIALS INDUSTRIES, INC.            Topic: DTRA05002

    In this SBIR Phase I/II effort, Structured Materials Industries, Inc. (SMI) will develop and demonstrate a thin film coating technology that can serve as both lethality enhancers and as functional coatings for munitions. The goal of this project is twofold: 1) we will fabricate and characterize reactive thin films that rapidly release large quantities of thermal energy and 2) we will develop a te ...

    SBIR Phase I 2005 Department of DefenseDefense Threat Reduction Agency
  8. Low Cost Manufacturing Process for Sodium Iodide Detectors

    SBC: XL Sci Tech Inc            Topic: DTRA05014

    An unconventional, continuous, and flexible manufacturing process is proposed for the production of sodium iodide detectors. The steps of crystal growing and substantially simplified detector machining are integrated into one streamline process based on proven techniques with minimal capital investment. This new production process will drastically reduce the manufacturing cost. A leading commerc ...

    SBIR Phase I 2005 Department of DefenseDefense Threat Reduction Agency
  9. Radiation Effects in Semiconductor Electronics

    SBC: Orora Design Technologies, Inc.            Topic: DTRA05001

    In this SBIR proposal, Orora Design Technologies, teaming up with Vanderbilt University and Oregon State University, and with the support from Boeing Solid-State Electronics, proposes to develop innovative mixed-mode (physics and device) and mixed-level(circuit and behavioral) simulation capacities for combined simulation of radiation and electrical performance to speed up simulation in rad hard d ...

    SBIR Phase I 2005 Department of DefenseDefense Threat Reduction Agency
  10. The development of a Single-Event upset immune, re-programmable and non-volatile field programmable gate array (r-NV-FPGA)

    SBC: STRUCTURED MATERIALS INDUSTRIES, INC.            Topic: MDA03056

    Radiation tolerant Field Programmable Gate Arrays (FPGA’s) have gained wide and rapid acceptance by military and aerospace equipment suppliers; however, there are presently a limited number of chip-sets available for production and they are limited to one time programming; hence if program changes are subsequently required a backup or chip replacement is required. The lack of FPGA alternatives ...

    SBIR Phase II 2005 Department of DefenseDefense Threat Reduction Agency
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