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Award Data
The Award database is continually updated throughout the year. As a result, data for FY24 is not expected to be complete until March, 2025.
Download all SBIR.gov award data either with award abstracts (290MB)
or without award abstracts (65MB).
A data dictionary and additional information is located on the Data Resource Page. Files are refreshed monthly.
The SBIR.gov award data files now contain the required fields to calculate award timeliness for individual awards or for an agency or branch. Additional information on calculating award timeliness is available on the Data Resource Page.
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Broadband Quadrature Mixers with Integrated I/Q Mismatch Calibration
SBC: CREONEX SYSTEMS INC. Topic: DMEA102002Communication SoC technology has advanced significantly over the past ten years resulting in highly integrated radio SoC chips for standards such as wireless Wi-Fi[xx], global position system (GPS), Bluetooth (BT), 3G cellular, digital TV (DTV), and cable modems. While most radio SoC’s are narrowband (e.g. WiFi, GPS, BT, and cellular), future trends favor broadband software defined radios (SDR) ...
SBIR Phase I 2010 Department of DefenseDefense Microelectronics Activity -
Broadband Quadrature Mixers and I/Q Mismatch Reduction
SBC: Tahoe RF Semiconductor Inc., Topic: DMEA102002Silicon on Sapphire technology offer several advantages over bulk CMOS and BiCMOS technologies for the design of RFICs (RF Integrated Circuits) for the System on Chip radio applications. These advantages include superior radiation hardness, improved isolation between circuits, higher efficiency amplifiers, and more bandwidth per cost. In the last few years, RFIC designers have favored are Zero-IF ...
SBIR Phase I 2010 Department of DefenseDefense Microelectronics Activity -
Low-noise amplifier (LNA) and Power amplifier (PA) for Radio-Frequency (RF) System-onChip (SoC) Applications on Silicon on Sapphire (SOS) Substrates
SBC: Tahoe RF Semiconductor Inc., Topic: DMEA092002Tahoe RF will design, simulate, fabricate and test a low noise amplifier (LNA) and companion power amplifier (PA). The feasibility study for this design was completed during the Phase I activities. The design will be fabricated using a noise improved device models of a 0.25 m silicon-on-sapphire (SOS) process.
SBIR Phase II 2011 Department of DefenseDefense Microelectronics Activity