You are here

Award Data

For best search results, use the search terms first and then apply the filters
Reset

The Award database is continually updated throughout the year. As a result, data for FY21 is not expected to be complete until September, 2022.

Download all SBIR.gov award data either with award abstracts (290MB) or without award abstracts (65MB). A data dictionary and additional information is located on the Data Resource Page. Files are refreshed monthly.

  1. Through-Lens Fiducial Marking System

    SBC: Checkpoint Technologies LLC            Topic: DMEA172002

    Awarded Phase I and having completed the Phase I concept and feasibility study of the innovative development of a tool, Thru-Lens Fiducial Marking, that can be integrated into an IR microscope that is able to create fiducial marks on the surface of the backside of silicon, we now propose to embark on Phase II, or implementation of said technology. The current state-of-art in semiconductor device ...

    SBIR Phase II 2019 Department of DefenseDefense Microelectronics Activity
  2. A Unified Blockchain for FPGA Firmware and Hardware

    SBC: Colvin Run Networks, Inc.            Topic: DMEA182003

    FPGA units in security-sensitive applications need secure manufacturing & configuration methods to combat supply chain interdiction and compromise by adversaries, with robust Third-Party IP provenance traceability. The proposed solution uniquely meets this need with a State of the Art blockchain implementation to build a fit-for-purpose supply chain blockchain (SCBC) optimized for DMEA’s FPGA  ...

    SBIR Phase I 2019 Department of DefenseDefense Microelectronics Activity
  3. Automated In-situ Large-area De-processing of ICs with High Throughput

    SBC: MICRONET SOLUTIONS INC.            Topic: DMEA18B001

    The objective of this proposal is to demonstrate the feasibility of producing an automated delayering and imaging system with end point detection, material density detection with built in neural network error correction. This process, coined fast Automated Delayering-Image Capture System (ADICS) leverages off of the existing Pix2Net which is a proven automated imaging 3D microchip reconstruction ...

    STTR Phase I 2019 Department of DefenseDefense Microelectronics Activity
  4. Handheld Liquid Particle Counter

    SBC: HAL Technology, LLC            Topic: DMEA182001

    The trend of microelectronic processing technology is for more advanced complex devices integrated in smaller size. Particles could become significantly more  prevalent as killer defects and have adverse effect on fabrication yield rate. Meanwhile, clean environment control requirements originally focused on particles in the air have been extended to encompass liquids that come into direct conta ...

    SBIR Phase I 2019 Department of DefenseDefense Microelectronics Activity
  5. High-brilliance Multi-Energy X-ray Source and Optics for Rapid IC Inspection

    SBC: Sigray, Inc.            Topic: DMEA162001

    This Phase II SBIR proposal aims to develop an x-ray illumination beam system comprising a dual-target x-ray source and a set of magnifying Wolter x-ray optics for use in laboratory-based integrated circuit (IC) inspection x-ray microscopes. Due to the increasing reliance on electronics for military systems and devices, a method to quickly analyze ICs in 3D is critical. X-ray microscopy enabled by ...

    SBIR Phase II 2019 Department of DefenseDefense Microelectronics Activity
  6. Laser Dithering Device for Handheld Liquid Particle Measurements

    SBC: Metrolaser, Inc.            Topic: DMEA182001

    We propose a hand-held device that would be capable of measuring particles as small as 20 nm in liquid batches from semiconductor fabrication. The proposed system will overcome the complexities of existing in-line and batch sampling techniques and thus would reduce the operating time and cost of the fabrication process. The device will be small and easily portable and will not come in direct cont ...

    SBIR Phase I 2019 Department of DefenseDefense Microelectronics Activity
  7. Front End of Line and Back End of Line Layer Fabrication Partitioning for the Purpose of Design Intellectual Property (IP) Protection

    SBC: MAXENTRIC TECHNOLOGIES, LLC            Topic: DMEA182002

    To meet the demands of the DMEA182-002 SBIR solicitation (“Front End of Line and Back End of Line Layer Fabrication Partitioning for the Purpose of Design Intellectual Property Protection”), the MaXentric and UCLA team proposes the HIGHFIVE (Heterogeneous Integration Guideline Highlighting Fabrication of Information Veiled Electronics), which provides a practical verification flow using the c ...

    SBIR Phase I 2019 Department of DefenseDefense Microelectronics Activity
  8. Vertical GaN transistors on bulk GaN substrates

    SBC: Avogy            Topic: 1

    In this abstract the development of vertical power transistors utilizing bulk GaN substrates with breakdown voltages of 1200V or higher, normally-off operation, and a drain current rating of 100A is proposed. These devices will feature vertical current flow, avalanche ruggedness, and a wide operating temperature range (-55 to 150°C). The target specific on-resistance for the transistor is 30x low ...

    SBIR Phase I 2013 Department of EnergyARPA-E
  9. Epitaxial GaN on flexible metal tapes for low-cost transistor devices

    SBC: IBEAM MATERIALS, INC.            Topic: 1

    GaN-based devices are the basis of a variety of modern electronics applications, especially in optoelectronics and high-frequency / high-power electronics. These devices are based on epitaxial films grown on single-crystal wafers. The single-crystal wafer substrates are limiting because of their size, expense, mechanical properties and availability. If one could make GaN-based devices over large a ...

    STTR Phase I 2013 Department of EnergyARPA-E
  10. Vertical GaN transistors on bulk GaN substrates

    SBC: Avogy            Topic: 1

    In this abstract the development of vertical power transistors utilizing bulk GaN substrates with breakdown voltages of 1200V or higher, normally-off operation, and a drain current rating of 100A is proposed. These devices will feature vertical current flow, avalanche ruggedness, and a wide operating temperature range (-55 to 150°C). The target specific on-resistance for the transistor is 30x low ...

    SBIR Phase II 2013 Department of EnergyARPA-E
US Flag An Official Website of the United States Government