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Award Data
The Award database is continually updated throughout the year. As a result, data for FY23 is not expected to be complete until September, 2024.
Download all SBIR.gov award data either with award abstracts (290MB)
or without award abstracts (65MB).
A data dictionary and additional information is located on the Data Resource Page. Files are refreshed monthly.
The SBIR.gov award data files now contain the required fields to calculate award timeliness for individual awards or for an agency or branch. Additional information on calculating award timeliness is available on the Data Resource Page.
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Nanomachine Device for Semiconductor Process Control Monitoring
SBC: XALLENT INC. Topic: NoneConventional characterization and test methods are increasingly ineffective when applied to structures less than 100 nanometers, causing challenges across R&D, process control and failure analysis. An increasing number of subtle defects become prominent drivers of failure as device size and operating margins decrease, e.g., processing anomalies in thin gate oxides, substrate problems related to do ...
SBIR Phase I 2019 Department of CommerceNational Institute of Standards and Technology -
A Tool for Building Semantically Interoperable Specification and Standards
SBC: XSB INC Topic: 9010273RStandards and specifications are widely used in government and industry to define requirements for products and processes and insure interoperability, safety, and quality of industrial and domestic products. Specifications and standards documents almost always cross-reference other standards and specification. Taken together, the web of interdependent standards forms an immensely important knowled ...
SBIR Phase I 2015 Department of CommerceNational Institute of Standards and Technology -
A Multi-Representation Architecture for STEP AP210-based PCB Stackup Design and Warpage Analysis
SBC: INTERCAX, LLC Topic: N/AThis effort creates foundations for highly automated simulation tools that predict warpage in printed circuit boards and assemblies (PCAs/PCBs) and chip packages. Our technique, MHS, provides core capabilities to automate warpage and other problems that were impractical until now. MHS extends a multi-representation approach the PI first conceived at Georgia Tech for CAD-CAE interoperability. This ...
SBIR Phase II 2006 Department of CommerceNational Institute of Standards and Technology