Award Data

Advanced Ceramic Fibers, LLC (ACF) completed the Navy SBIR Phase I Base Program and clearly demonstrated the feasibility of our approach to create a truly robust composite for turbine engines that exceeds the known boundaries for ceramic composites and the Navy performance objectives for this Topic. Our engineered materials approach involved in-depth background experience in ceramic matrix composi ...

Idaho Scientific proposes to design and develop, SPUD, an irrefutable tamper logging protocol.During the course of this Phase I effort, Idaho Scientific will implement the core of the logging protocol and develop a set of unit tests designed to evaluate properties of that protocol that uphold its irrefutable claims. During a Phase II effort, Idaho Scientific would propose to encapsulate this proto ...

Idaho Scientific proposes the development of Secure Protocol Unalterable Data (SPUD) as a means to identify activity against system technologies. Approved for Public Release | 17-MDA-9219 (31 May 17)

UNIFORM LARGE AREA, DEVICE QUALITY INDIUM PHOSPHIDE (INP) EPITAXIAL LAYERS ON INSULATING SUBSTRATES COULD LEAD TO THE DEVELOPMENT OF A NEW GENERATION OF PRODUCIBLE, RADIATION-HARDENED MICROELECTRONIC AND OPTOELECTRONIV INTEGRATED CIRCUITS. INP ALLOYS OFFER THE ADVANTAGES OF: PROVEN RESISTANCE TO RADIATION DAMAGE; LOWER SURFACE RECOMBINATION THAN GAAS; HIGH PEAK ELECTRON VELOCITY; AND BANDGAPS THAT ...

ABSTRACT: The past decade has seen a proliferation of computing devices. A landscape once dominated by single core microprocessors has given way to a plethora of competing technologies including multicore x86, ARM, and Power-family processors, graphics processing units (GPUs), field-programmable gate arrays (FPGAs), Xeon Phis, DSPs, and TILE architectures, among others. Further complicating matter ...

Developers of modern software, particularly those targeting mobile or embedded platforms, are presented with a wide variety of hardware choices. Solutions can be built on microprocessors (e.g. x86, ARM, or Power architecture), GPUs (e.g. NVIDIAs Tegra), DSPs, FPGAs, or some combination of these technologies. Not only does this place a significant burden on programmers in understanding the intricac ...

In this STTR effort we will develop key packaging techniques for wafer-level hybrid electrical-optical co-packaging based on silicon photonic platform. These techniques include packaging LiNbO3 modulator on insulator (LNOI), high-speed modified uni-traveling carrier (MUTC) photodiodes packaging and high-efficiency fiber coupling. Silicon is the desired host material for photonic integrated circuit ...