High-Speed Metallic Interconnects Technology

Award Information
Agency:
Department of Defense
Branch
Defense Advanced Research Projects Agency
Amount:
$99,000.00
Award Year:
2005
Program:
SBIR
Phase:
Phase I
Contract:
W31P4Q-06-C-0106
Award Id:
74329
Agency Tracking Number:
05SB2-0337
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
2953 Bunker Hill Lane, Suite 400, Santa Clara, CA, 95054
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
125981485
Principal Investigator:
AchyutDutta
CTO
(408) 282-3628
akdutta@banpil.com
Business Contact:
AchyutDutta
President / CTO
(408) 282-3628
akdutta@banpil.com
Research Institute:
n/a
Abstract
With the continued growth in the integration density of CMOS (complementary metal-oxide semiconductor) technology and clock frequency of microprocessors, the aggregate bandwidth required between future-generation microprocessors and chipsets will increase sharply. Driving serial or parallel data at high speed over copper on FR4 based printed circuit boards (PCBs) is becoming a severe design constraint. This limits the signal carrying capacity significantly for a given channel length. Innovative high-speed electrical off-chip interconnects technology is highly desirable, which can reduce the disparity between off-chip and on-chip signal carrying capacity in cost-effective and reliable ways. We propose an innovative cost-effective high speed (> 20Gb/s per channel) FR4 based electrical (metallic) interconnect technology, which can increase the signal carrying capacity of the board-level interconnects more than 6 times than the conventional FR4 technology. During Phase I, we propose to carry out: (i) identifying system applications where high speed metallic interconnects can be used, (ii) design and model the proposed metallic interconnects and simulate their performances, (iii) investigate the high-speed chips capable to handle over 10 Gb/s per channel and design the interfaces and circuitry for board demonstration, (iv) build the board with high speed chip attached, and test the performances, and (v) analyze and optimize the design. Details structure simulation, design optimization, and board demonstration, done in Phase II, can be connected to Phase II work. We will focus primarily on manufactruring technology development for more than 8 layers FR4-PCB buildup and demonstrate prototype with multiple chips attached in Phase-II.

* information listed above is at the time of submission.

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