SBIR Phase I: Innovative High Speed Electrical Chip-to-Chip Interconnects for Next Generation Systems

Award Information
Agency: National Science Foundation
Branch: N/A
Contract: 0539139
Agency Tracking Number: 0539139
Amount: $99,990.00
Phase: Phase I
Program: SBIR
Awards Year: 2006
Solicitation Year: 2005
Solicitation Topic Code: EL
Solicitation Number: NSF 05-557
Small Business Information
Banpil
2953 Bunker Hill Lane, Santa Clara, CA, 95054
DUNS: N/A
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: Y
Principal Investigator
 Achyut Dutta
 Dr
 (408) 282-3628
 akdutta@banpil.com
Business Contact
 Achyut Dutta
Title: Dr
Phone: (408) 282-3628
Email: akdutta@banpil.com
Research Institution
N/A
Abstract
This SBIR Phase I project proposes chip-to-chip interconnects that can be applied in the mother boards/ backplanes of high performance networking systems and/or computing systems, where 10 Gb/s and beyond signal speed per channel (serial) is necessary. An innovative cost-effective high speed (> 20Gb/s per channel) electrical interconnect technology, which can increase the signal carrying capacity of the board-level interconnects more than 6 times than the conventional technology is proposed. This can help to route the signal longer distances (at given signal-speed) at lower cost by using standard dielectric material. The company will investigate the design, feasibility of the concept, process development, and data analysis approaches in order to create a high speed interconnect PCB board, and each can carry the signal as high as 20 Gb/s. The proposed high speed electrical chip-to-chip interconnects will have applications in high speed PCs, high-speed servers, networking systems, gaming machines, communications systems, imaging and video systems.

* information listed above is at the time of submission.

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