SBIR Phase I: Ge-Free Strained Silicon Via dTCE Bonding (Differential Thermal Coefficient of Expansion Bonding)

Award Information
Agency: National Science Foundation
Branch: N/A
Contract: 0314300
Agency Tracking Number: 0314300
Amount: $99,880.00
Phase: Phase I
Program: SBIR
Awards Year: 2003
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
386 Spanish Wells Road, Hilton Head Island, SC, 29926
DUNS: N/A
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Rona Belford
 () -
Business Contact
Phone: () -
Research Institution
N/A
Abstract
This Small Business Innovation Research (SBIR) Phase I propose to combine the technologies of silicon-on-insulator (SOI) manufacture with strain-inducing wafer bonding to produce Strained-Si On Insulator (SSOI) wafers. Silicon-based devices with silicon/germanium (Si/Ge) heterostructures have been extensively researched and this has lead to the discovery that tensile strained silicon exhibits superior electronic properties. Bi axially strained-silicon devices are currently strained via expensive which is a highly technical heterostructure fabrication process. Tensile strain can be introduced by growing silicon pseudomorphically on to a lattice of larger unit cell, usually an alloy of Ge/Si. In this work, it is hoped that by optimizing Strained-Silicon-on-Insulator will increase carrier mobilities by more than 3 times The anticipated benefits of this technology would yield ultra-fast, mainstream silicon-based electronics, which would effectively be new host materials with speed, and performance would surpass Gallium Arsenate (GaAs). The multi-billion dollar chips industry would benefit would benefit by reducing the costs for a new plant to design technology.

* Information listed above is at the time of submission. *

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