SBIR Phase I: Ge-Free Strained Silicon Via dTCE Bonding (Differential Thermal Coefficient of Expansion Bonding)
Small Business Information
386 Spanish Wells Road, Hilton Head Island, SC, 29926
AbstractThis Small Business Innovation Research (SBIR) Phase I propose to combine the technologies of silicon-on-insulator (SOI) manufacture with strain-inducing wafer bonding to produce Strained-Si On Insulator (SSOI) wafers. Silicon-based devices with silicon/germanium (Si/Ge) heterostructures have been extensively researched and this has lead to the discovery that tensile strained silicon exhibits superior electronic properties. Bi axially strained-silicon devices are currently strained via expensive which is a highly technical heterostructure fabrication process. Tensile strain can be introduced by growing silicon pseudomorphically on to a lattice of larger unit cell, usually an alloy of Ge/Si. In this work, it is hoped that by optimizing Strained-Silicon-on-Insulator will increase carrier mobilities by more than 3 times The anticipated benefits of this technology would yield ultra-fast, mainstream silicon-based electronics, which would effectively be new host materials with speed, and performance would surpass Gallium Arsenate (GaAs). The multi-billion dollar chips industry would benefit would benefit by reducing the costs for a new plant to design technology.
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