BINACHIP, INC.

Basic Information

203 N. Wabash Av.
SUITE 203
Chicago, IL, 60601

Company Profile

n/a

Additional Details

Field Value
DUNS: 134656532
Hubzone Owned: N
Socially and Economically Disadvantaged: N
Woman Owned: N
Number of Employees: 3


  1. FPGA Low Power Design Rules

    Amount: $69,993.00

    Commercial FPGA programming software tools use logic synthesis tools to route the connections between logic gates, look-up tables, and memory units. Current commercial tools, however, are optimized to ...

    SBIR Phase I 2010 Army Department of Defense
  2. A High Level Synthesis Tool for FPGA Design from Software Binaries

    Amount: $749,499.00

    Many DOD systems require high-performance digital signal processing and image processing functions that cannot be implemented efficiently on conventional microprocessors. Systems engineers often addre ...

    SBIR Phase II 2009 Defense Advanced Research Projects Agency Department of Defense
  3. A High Level Synthesis Tool for FPGA Design from Software Binaries

    Amount: $98,640.00

    Many DOD systems require advanced digital signal processing and image processing functions that cannot be efficiently implemented on conventional micro-processors, hence designers have started mapping ...

    SBIR Phase I 2007 Defense Advanced Research Projects Agency Department of Defense
  4. A Hardware/Software Design Environment for Reconfigurable Communication Systems

    Amount: $600,000.00

    NASA's vision of Space Exploration will require advancements in communication systems to maintain flexibility and adaptability to changing needs and requirements. The research outlined in this project ...

    SBIR Phase II 2007 National Aeronautics and Space Administration
  5. SBIR Phase I: Automated Design Environment for Embedded Systems

    Amount: $100,000.00

    This Small Business Innovation Research (SBIR) Phase I project develops an automated compiler to translate software binary and assembly code of a general-purpose DSP processor into Register Transfer L ...

    SBIR Phase I 2006 National Science Foundation
  6. A Hardware/Software Design Environment for Reconfigurable Communication Systems

    Amount: $69,300.00

    NASA's vision of Space Exploration will require advancements in communication systems to maintain flexibility and adaptability to changing needs and requirements. The research outlined in this project ...

    SBIR Phase I 2006 National Aeronautics and Space Administration
  7. A System Level Tool for Translating Software to Reconfigurable Hardware

    Amount: $100,000.00

    In this research we will develop a system level tool to translate binary code of a general-purpose processor into Register Transfer Level VHDL code to be mapped onto FPGA-based reconfigurable hardware ...

    STTR Phase I 2005 National Aeronautics and Space Administration

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