SBIR Phase I: Automated Design Environment for Embedded Systems

Award Information
Agency: National Science Foundation
Branch: N/A
Contract: 0609666
Agency Tracking Number: 0609666
Amount: $100,000.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: EO
Solicitation Number: NSF 05-605
Solicitation Year: 2005
Award Year: 2006
Award Start Date (Proposal Award Date): N/A
Award End Date (Contract End Date): N/A
Small Business Information
2130 Chandler Lane, Glenview, IL, 60026
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 David Zaretsky
 (773) 248-4484
Business Contact
 Prith Benerjee
Phone: (847) 757-8708
Research Institution
This Small Business Innovation Research (SBIR) Phase I project develops an automated compiler to translate software binary and assembly code of a general-purpose DSP processor into Register Transfer Level VHDL and Verilog code for subsequent mapping onto FPGA hardware. Recent advances in embedded communications and control systems for personal and vehicular environments are driving efficient hardware and software implementations of complete systems-on-chip (SOC). As part of this study, novel algorithms will be developed for alias analysis, data flow analysis, automatic identification of loops and other control constructs, and procedure call recovery. Furthermore, techniques for performing hardware/software co-design will be investigated on integrated Systems-on-a-Chip (SOC) platforms consisting of embedded processors, memories, and FPGAs. The concepts developed as part of this research will be demonstrated using a prototype compiler that will translate binary code of off-the-shelf processors into a hardware/software implementation on standard FPGAs. The development of a system level tool for designing DSP will reduce design times from months to days. Such a compiler will allow software developers to reuse millions of lines of software developed in the past for general-purpose DSP processors, and migrate them painlessly to newer SOC platforms. There is a large established code base of DSP algorithms that are optimized for DSP processors. The compiler will take these DSP implementations in assembly and generate implementations in hardware in the form of FPGAs and SOCs automatically. Furthermore, if DSP engineers wish to have an automated path from higher-level languages such as C, C++, and MATLAB to hardware, they can use currently available tools to compile these languages to the assembly level of a general-purpose processor, and then use the proposed compiler to map these assembly codes onto FPGAs and SOCs.

* Information listed above is at the time of submission. *

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