A Hardware/Software Design Environment for Reconfigurable Communication Systems

Award Information
Agency:
National Aeronautics and Space Administration
Branch:
N/A
Amount:
$69,300.00
Award Year:
2006
Program:
SBIR
Phase:
Phase I
Contract:
NNC06CA60C
Agency Tracking Number:
053196
Solicitation Year:
2005
Solicitation Topic Code:
O1.06
Solicitation Number:
N/A
Small Business Information
Binachip, Inc.
2130 Chandler Lane, Glenview, IL, 60026-5744
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
134656532
Principal Investigator
 David Zaretsky
 Principal Investigator
 (847) 757-8708
 dcz@northwestern.edu
Business Contact
 Prith Banerjee
Title: Chairman and Chief Scientist
Phone: (847) 757-8708
Email: prith@uic.edu
Research Institution
N/A
Abstract
NASA's vision of Space Exploration will require advancements in communication systems to maintain flexibility and adaptability to changing needs and requirements. The research outlined in this project will develop a hardware/software design environment that will allow NASA engineers to automatically develop flexible, reconfigurable communications systems. We will develop automated compiler algorithms to translate software code available in a variety of high level languages (C/C++/SIMULINK) and assembly of various general purpose processors into Register Transfer Level VHDL code to be mapped onto FPGA-based hardware. We further plan to study techniques for performing hardware/software co-design on integrated systems-on-a-chip platforms consisting of embedded processors, memories and FPGAs. We will demonstrate our concepts using a prototype compiler that will translate software implementations of communications applications into a hardware/software implementation on a Xilinx Virtex II Pro Platform FPGA and a DINI DN2000k10 board. The proposed work is revolutionary and addresses NASA's Space Exploration needs as follows: (1) it will develop a system level tool for designing hardware systems which will reduce design times from months to days (2) it will enable the use of cost-efficient, high-performance FPGAs (3) it will allow engineers to reuse of millions of lines of software developed in the past for general purpose processors, and migrate them painlessly to newer SOC platforms.

* information listed above is at the time of submission.

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