A System Level Tool for Translating Software to Reconfigurable Hardware

Award Information
Agency: National Aeronautics and Space Administration
Branch: N/A
Contract: NNA05AC26C
Agency Tracking Number: 040009
Amount: $100,000.00
Phase: Phase I
Program: STTR
Awards Year: 2005
Solicitation Year: 2004
Solicitation Topic Code: T1.01
Solicitation Number: N/A
Small Business Information
2130 Chandler Lane, Glenview, IL, 60026-5744
DUNS: 134656532
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: Y
Principal Investigator
 Prith Banerjee
 Principal Investigator
 (847) 757-8708
 prith@uic.edu
Business Contact
 Prith Banerjee
Title: Chairman and President
Phone: (847) 757-8708
Email: prith@uic.edu
Research Institution
 University of Illinois at Chicago
 Prith Banerjee
 851 South Morgan St.
Chicago, IL, 60607
 (847) 757-8708
 Domestic nonprofit research organization
Abstract
In this research we will develop a system level tool to translate binary code of a general-purpose processor into Register Transfer Level VHDL code to be mapped onto FPGA-based reconfigurable hardware. We further plan to study techniques for performing hardware/software co-design on integrated systems-on-a-chip platforms consisting of embedded processors, memories and FPGAs. Finally we will develop techniques to perform area, delay and power tradeoffs in the hardware that is synthesized by our compiler on the FPGAs. We will demonstrate our concepts using a prototype compiler that will translate binary code of a Texas Instrument TMS320 C6000 processor into a hardware/software implementation on a Xilinx Virtex II Pro Platform FPGA. This work will be performed jointly between BINACHIP, a small business company, and University of Illinois at Chicago, a partner research institution

* Information listed above is at the time of submission. *

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