A High Level Synthesis Tool for FPGA Design from Software Binaries

Award Information
Agency:
Department of Defense
Branch
Defense Advanced Research Projects Agency
Amount:
$98,640.00
Award Year:
2007
Program:
SBIR
Phase:
Phase I
Contract:
W31P4Q-07-C-0094
Award Id:
81230
Agency Tracking Number:
06SB2-0095
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
2130 Chandler Lane, Glenview, IL, 60026
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
134656532
Principal Investigator:
David Zaretsky
Senior Software Engineer
(224) 420-0759
david@binachip.com
Business Contact:
Prith Banerjee
Chairman and Chief Scient
(847) 757-8708
prith@uic.edu
Research Institution:
n/a
Abstract
Many DOD systems require advanced digital signal processing and image processing functions that cannot be efficiently implemented on conventional micro-processors, hence designers have started mapping these applications onto FPGAs. However, most FPGA implementations are manually designed and highly coupled to the hardware, often taking advantage of special hardware features of the target FPGA. The manual design of such highly optimized hardware on FPGAs requires design times of the order of months. In this research, we propose a novel methodology and system level tool to design applications on FPGAs by taking software specifications in the form of binary and assembly implementation on a conventional microprocessor, performing high-level synthesis, and automatically generating Register Transfer Level (RTL) VHDL and Verilog code. The RTL code can be synthesized by commercial backend logic synthesis and physical synthesis tools automatically onto FPGAs This revolutionary methodology can reduce the design times for new hardware designs and hardware upgrades from months to hours. The RTL code that is synthesized can be automatically verified for correctness using a simulation based methodology that creates the testbenches and proves the bit-true correctness of the synthesized hardware. As part of this automated flow, our system-level design tool will provide the user with high-level estimates of area, delay and power consumption using which various design tradeoffs can be rapidly explored by the designer.

* information listed above is at the time of submission.

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