A High Level Synthesis Tool for FPGA Design from Software Binaries

Award Information
Agency: Department of Defense
Branch: Defense Advanced Research Projects Agency
Contract: W31P4Q-09-C-0286
Agency Tracking Number: 06SB2-0095
Amount: $749,499.00
Phase: Phase II
Program: SBIR
Awards Year: 2009
Solitcitation Year: 2006
Solitcitation Topic Code: SB062-006
Solitcitation Number: 2006.2
Small Business Information
Binachip, Inc.
203 N. Wabash Av., SUITE 203, Chicago, IL, 60601
Duns: 134656532
Hubzone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 David Zaretsky
 (312) 346-5660
Business Contact
 Prith Banerjee
Title: Chairman
Phone: (847) 757-8708
Email: prith@binachip.com
Research Institution
Many DOD systems require high-performance digital signal processing and image processing functions that cannot be implemented efficiently on conventional microprocessors. Systems engineers often address these issues by mapping the compute-intensive portions of these applications onto FPGAs in the form of hardware accelerators, as part of a hardware-software co-design. However, a manual hardware implementation of a highly optimized FPGA design may require design times on the order of months, especially if the designers take advantage of advanced features available on many FPGA devices. In this work, we have propose a novel methodology and system level tool, BINACHIP FPGA, which generates hardware-software co-design applications by taking software applications in the form of binary and assembly code on a conventional microprocessor, perform high-level synthesis, and automatically generate Register Transfer Level (RTL) VHDL and Verilog code. The RTL code can be synthesized by commercial backend logic synthesis and physical place and route tools for implementation on an FPGA in the form of a hardware accelerator. The RTL code can be verified with a testbench that is automatically generated by the tool, using a simulation based methodology to verify the bit-true accuracy of the synthesized hardware. This revolutionary methodology can reduce the design times for new hardware-software co-designs from months to hours. The objectives of the Phase II research will be to study the following topics: • Automated Hardware/Software Partitioning • Advanced Streaming Architectures • System Level Design Environment on Large Applications

* information listed above is at the time of submission.

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