MUCOSAL IRON UPTAKE AND TRANSFER IN HEMOCHROMATOSIS

Award Information
Agency: Department of Health and Human Services
Branch: N/A
Contract: N/A
Agency Tracking Number: 1R43DK055904-01
Amount: $116,664.00
Phase: Phase I
Program: SBIR
Awards Year: 1999
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
2201 W CAMPBELL PARK DR, CHICAGO, IL, 60612
DUNS: N/A
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 MORTEZA JANGHORBANI
 () -
Business Contact
Phone: (312) 649-8160
Email: DCRIBBS@FULLNET.COM
Research Institution
N/A
Abstract
Not Available With the increasing consumer demand for mobile/portable systems, low power VLSI has gained great importance. A number of circuit level power reduction schemes, including supply/threshold voltage scaling, multiple threshold schemes and selective clocking are available. However, greater power reduction can be achieved only if the problem is approached from a global perspective. This includes algorithmic, architectural and circuit levels. Further, significant power reduction has been observed when system-level improvements are applied. Primary among these is the software-level power efficiency. This involves performing a power spectrum analysis of the instruction set of the target processor, followed by an analysis of the assembly code for the target application. Power-hungry instructions are replaced with more efficient ones. At the architectural level, bus-encoding schemes can be applied to reduce the impact of switching at the large capacitances associated with the I/O pads. These methods include data- compression and coding schemes such as bus-invert coding. At the circuit-level, adaptive voltage scaling, in conjunction with self-timed approaches, offer great promise. Strong ARM processor has very good low-power characteristics that makes it an attractive target architecture. A synchronous ARM, integrated with a DSP core can offer high speed DSP solutions with significant power reduction. The techniques developed in Phase-I will be applied to an asynchronous ARM DSP s

* Information listed above is at the time of submission. *

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