STTR PHASE I: Blended Clocked and Clockless Integrated Circuit Systems

Award Information
Agency:
National Science Foundation
Branch
n/a
Amount:
$149,709.00
Award Year:
2008
Program:
STTR
Phase:
Phase I
Contract:
0741055
Award Id:
88510
Agency Tracking Number:
0741055
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
11520 St. Charles Rock Road, Bridgeton, MO, 63044
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
800211083
Principal Investigator:
Jerome Cox
DSc
(314) 738-0403
jcox@blendics.com
Business Contact:
Jerome Cox
DSc
(314) 738-0403
jcox@blendics.com
Research Institute:
Southern Illinios University Edwardsville
Stephen Hansen
P.O. Box 1454
Rendleman Hall, Rm. 2207
Edwardsville, IL, 62026 1801
(618) 650-3010
Nonprofit college or university
Abstract
This Small Business Technology Transfer Phase I research project will demonstrate a globally asynchronous, locally synchronous (GALS) methodology for the design of large-scale, deep-submicron, System-on-Chip (SoC) integrated circuits fabricated in Field-Programmable Gate Arrays (FPGAs). The methodology utilizes a Delay-Insensitive (DI) interconnect between conventionally clocked subsystems. The interconnect components are bundled data paths and a set of control elements whose designs are DI and hazard-free across processes and submicron scaling. These control elements are defined by Petri net models or their trace theory equivalents. Prototype software has been developed to synthesize, from their defining models, the required logic for these elements. Hazards are identified, logic hazards eliminated and metastability hazards managed. The methodology, in contrast to other approaches, allows the synthesis of a variety of arbiters from their models and includes novel stability detectors that can be implemented in FPGAs. The proposed work will improve the reliability, breadth and ease-of-use of the synthesis software and demonstrate a significant multiprocessor FPGA architecture. The proposed integrated circuit design methodology can substantially decrease the difficulty of designing billion-transistor, integrated-circuits for the SoCs of the future. The proposed GALS methodology will be introduced in the increasingly popular FPGA sector where other clockless designs have failed to leave the research laboratories. The proposed methodology has the potential to markedly decrease design cost and time-to-market of the large, specialized systems of the future.

* information listed above is at the time of submission.

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