A VLSI DIGITAL TESTER BASED UPON A SINGLE CUSTOM CHIP PER INDIVIDUAL PIN

Award Information
Agency:
National Aeronautics and Space Administration
Branch
n/a
Amount:
$50,000.00
Award Year:
1987
Program:
SBIR
Phase:
Phase I
Contract:
n/a
Agency Tracking Number:
5119
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
Bonneville Scientific Inc
918 East 900 South, Salt Lake City, UT, 84105
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
n/a
Principal Investigator:
() -
Business Contact:
Allen R. Grahn
Investigator
() -
Research Institution:
n/a
Abstract
IN THIS PHASE I, SIX-MONTH FEASIBILITY STUDY WE PROPOSE TO GENERATE A PLAN FOR A SYSTEM ARCHITECTURE FOR A DIGITAL VLSI CHIP TESTER. THE TESTER WILL BE DESIGNED TO INTERFACE TO THE DESIGN WORKSTATION TO ALLOW INTERACTIVE DEBUGGING OF PROTOTYPE CIRCUITS AND SUBSEQUENT DOWN LOADING OF TEST PATTERNS AND EXPECTED RESULTS TO A PRODUCTION VLSI TESTER. THE TESTER WILL BE LOW IN COST BECAUSE IT WILL NOT PERFORM ANALOG TESTING AND BECAUSE EACH INDIVIDUAL PIN OF THE DEVICE UNDER TEST WILL BE DIRECTLY TESTED BY A DEDICATED TESTING INTEGRATED CIRCUIT. THE FUNCTIONAL DESIGN OF THIS TESTING CHIP WILL BE GENERATED, THE CIRCUIT WILL BE COMPLETELY DESIGNED USING PATH PROGRAMMABLE LOGIC, AND IT WILL BE SIMULATED DURING PHASE I. THE CHIP WILL BE FABRICATED AND THE COMPLETE TESTER SYSTEM (HARDWARE AND SOFTWARE) WILL BE COMPLETED IN PHASE II.

* information listed above is at the time of submission.

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