Random Number Generation for High Performance Computing

Award Information
Agency: Department of Defense
Branch: Army
Contract: W911NF-11-C-0026
Agency Tracking Number: A10A-012-0292
Amount: $99,965.00
Phase: Phase I
Program: STTR
Awards Year: 2010
Solicitation Year: 2010
Solicitation Topic Code: A10A-T012
Solicitation Number: 2010.A
Small Business Information
Silicon Informatics, Inc.
6500 Parnell Ave, Edina, MN, 55435
DUNS: N/A
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Rajendra Boppana
 Professor
 (210) 458-5692
 boppana@cs.utsa.edu
Business Contact
 Robert Keller
Title: President and CEO
Phone: (612) 327-0682
Email: rkeller@siliconinformatics.com
Research Institution
 Univ of Texas at San Antonio
 Noe Saldana
 Office of Sponsored Programs
One UTSA Circle
San Antonio, TX, 78248
 (210) 458-4340
 Nonprofit college or university
Abstract
Highly scalable parallel random number generators (RNGs) will be developed, evaluated and implemented for use in high performance computing on thousands of multi-core processors and general purpose graphics processing units. The main contributions are: (a) design and implementation of new parallel test methods that capture the inter-stream correlations exhibited in practice and complement the currently widely used sequential test batteries, (b) development of new parallel RNGs that produce 100s of thousands of high quality individual random number streams and explicitly minimize inter-stream correlations, and (c) preliminary implementation of the new test methods and parallel RNGs. The proposed RNGs will also be evaluated and tuned to generate cryptographically-secure random number streams that resist cryptanalysis attacks by insiders and eavesdroppers when used in large-scale peer-to-peer and distributed security applications. The investigators have extensive experience in the applications of random number generators, the test methods for random number generators, and the implementation of Monte Carlo applications on large clusters of processors and graphics processing units. The proposed approach balances the theoretical research with the implementation efficiencies and the use in real applications.

* information listed above is at the time of submission.

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