High-Sample Rate Analog to Digital Converters for Reconfigurable Phased Array Applications

Award Information
Agency: Department of Defense
Branch: Defense Advanced Research Projects Agency
Contract: D16PC00100
Agency Tracking Number: D153-004-0079
Amount: $154,948.34
Phase: Phase I
Program: SBIR
Solicitation Topic Code: SB153-004
Solicitation Number: 2015.3
Solicitation Year: 2016
Award Year: 2016
Award Start Date (Proposal Award Date): 2016-04-05
Award End Date (Contract End Date): 2017-04-21
Small Business Information
398 South Mill Ave, Suite 302, Tempe, AZ, 85281
DUNS: 078602532
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Esko Mikkola
 (520) 647-4445
Business Contact
 Esko Mikkola
Phone: (520) 647-4445
Email: engineering@alphacoreinc.com
Research Institution
This SBIR Phase I proposal requests support for Alphacore, Inc. to design and characterize a 40Gsps (giga-samples per-second), 7-bit (ENOB > 6 bits), low-power (<500mW) analog-to-digital converter (ADC) for use in configurable phased array applications in the defense sector.The proposed ADC employs an innovative topology with high-bandwidth front-end sampling circuit combined with an interpolated flash-type ADC. Innovative and effective digital calibration is used to guarantee spurious free Nyquist frequency band which is an important requirement in phased array applications.The design will be implemented in a 28nm fully depleted silicon on insulator (FDSOI) CMOS technology.The maximum sampling rate of Alphacores ADC is 48 GS/s, resolution is 7-bits (effective number of bits, ENOB = 6.0 bits) and the power consumption is 480mW, not counting the consumption of the output interface. The ADC has analog input bandwidth of 33GHz. The sampling speed, ENOB and power have all been measured from transistor level schematic simulations, and are to a large part based on netlists extracted from layouts.

* Information listed above is at the time of submission. *

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