Integrated Thermal Management and Wafer-Scale Packaging for High-Power VCSELs

Award Information
Agency: Department of Defense
Branch: Missile Defense Agency
Contract: HQ0147-10-C-7201
Agency Tracking Number: B08B-011-0109
Amount: $749,993.00
Phase: Phase II
Program: STTR
Awards Year: 2010
Solicitation Year: 2008
Solicitation Topic Code: MDA08-T011
Solicitation Number: 2008.B
Small Business Information
Aerius Photonics, LLC.
2223 Eastman Ave., Suite B, Ventura, CA, 93003
DUNS: 145925520
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: Y
Principal Investigator
 Chad Wang
 Research Scientist
 (805) 642-4645
 cswang@aeriusphotonics.com
Business Contact
 Jon Geske
Title: President
Phone: (805) 642-4645
Email: geske@aeriusphotonics.com
Research Institution
 Boise State University
 Karen Henry
 1910 University Drive
MS 1135
Boise, ID, 83725
 (208) 426-1574
 Nonprofit college or university
Abstract
Aerius Photonics is proposing to develop high-power Vertical Cavity Surface Emitting Lasers (VCSELs) and arrays on 4” substrates with an integrated thermal management approach to improve the thermal performance on an entirely wafer-level manufacturing compatible process. This is critical as waste heat and wafer-scale manufacturing approaches are driving factors for performance and costs in a laser diode, especially diode pumped solid-state laser systems relevant to the US BMDS. The performance of the high-power diode laser is limited by the ability of the packaging to extract heat away from the laser’s active region, where the majority of the heat is generated. If the heat is not removed, the gain, and subsequently the output power and efficiency of the laser and entire system are decreased. In this proposal, Aerius will develop a wafer-scale compatible process on 4” substrates with improved thermal performance for high power VCSEL arrays. This approach will further improve the thermal performance and manufacturability of VCSEL technology and offer a 50% reduction in the laser diode heating by improving the waste heat transport and spreading from the semiconductor chip to the thermal management system.

* information listed above is at the time of submission.

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