COLLABORATIVE DEVELOPMENT PROJECTS

Description:

Please Note that a Letter of Intent is due Tuesday, September 05, 2017

PROGRAM AREA OVERVIEW: OFFICE OF ADVANCED SCIENTIFIC COMPUTING RESEARCH 

Maximum Phase I Award Amount: $225,000

Maximum Phase II Award Amount: $1,500,000

Accepting SBIR Applications: YES

Accepting STTR Applications: YES

 

The Office of Advanced Scientific Computing Research program office is actively engaged in the development of next generation leadership class supercomputers. This topic solicits proposals that require a collaborative team of small businesses combining their different expertise’s to develop more complex and operational subsystems or software modules for these emerging supercomputers. A collaborative team approach, with up to five small businesses forming this team, will receive funding under this topic.

a. Photonic-Storage Subsystem Input/Output (P-SSIO) Interface

Over the past decade, numerous studies have shown that to be affordable, future supercomputers will have electric power limit of approximately 20 MW. This limitation will place a significant constraint on the I/O and memory subsystems due to the high cost of moving bits between system ICs (CPU, Memory, Bus controller, etc.). Replacing the electrical components of the Peripheral Component Interconnect Express (PCIe) Physical layer (copper traces, connectors, switches, etc.) with photonic based components would greatly increase the I/O and peripheral device bandwidth capacity of the supercomputer without exceeding the expected power budget. This topic seeks a collaborative team of small businesses to design, fabricate, build, and test a photonic based PCIe physical layer Storage Subsystem I/O interface that meets the following specifications.

  • 4-8 Server class PCIe version 4.0 x32 controller chips (CPU or dedicated controller)
  • 16 – 32 Non-Volatile Memory Express (NVMe) based Storage Subsystems connected at 16 GT/s I/O rate each
  • Simultaneous access from every PCIe controller to multiple NVMe storage devices (256 GB/s aggregate I/O rate with 4 PCIe controllers)
  • WDM optical transceivers matched to the PCIe I/O v 4.0 transmission rates
  • Reconfigurable optical interconnect fabric
  • Low loss Optical connectors and/or integrated Micro Optical Bench assemblies

The photonic components of the P-SSIO must be capable of operating on 0.5 pJ/b of power (not counting the PCIe or NVMe Controller or Storage Device electrical power). Storage devices (SSD) may be located up to 20 meters distant from the PCIe controller.

It is expected that a collaborative team of businesses will work together to design and build this P-SSIO device. Each business may include one or more academic or lab partners as subcontractors. Each business must submit a proposal that contains an identical narrative section and a common statement describing how any Intellectual Property issues will be addressed by the collaboration. Each proposal must have business specific budget and budget justification forms, biographical data for the Principal Investigator and senior personnel involved in the project, and commercialization plan. The title page for each submission must clearly show all businesses involved in the collaboration.

Questions – Contact: Richard Carlson, Richard.Carlson@science.doe.gov

 

b. Other

In addition to the specific subtopic listed above, the Department invites grant applications in other areas that fall within the scope of the topic description above.

Questions – Contact: Richard Carlson, Richard.Carlson@science.doe.gov

References:

1. Bahadori, M., Rumley, S., Nikolova, D., Bergman, K., Comprehensive Design Space Exploration of Silicon Photonic Interconnects, IEEE Journal of Lightwave Technology, Vol. 34, Issue 12, p. 2975-2987.

http://lightwave.ee.columbia.edu/files/Bahadori2015b.pdf

2. Rumley, S., Nikolova, D., Hendry, R., et al., 2015, Silicon Photonics for Exascale Systems [Invited Tutorial], Journal of Lightwave Technology, Vol. 33, Issue 3.

http://lightwave.ee.columbia.edu/files/Rumley2015.pdf

3. Biberman, A., Bergman, K., 2012, Optical Interconnection Networks for High-performance Computing Systems [invited]," Reports on Progress in Physics, Vol. 75, p. 15.

http://lightwave.ee.columbia.edu/files/Biberman2012.pdf

4. Liboiron-Ladouceur, O., Wang, H., Garg, A., Bergman, K., 2009, Low-poser, Transparent Optical Network Interface for High Bandwidth Off-chip Interconnects, Optics Express, Vol. 17, Issue 8, pp. 6550-6561. https://www.osapublishing.org/oe/abstract.cfm?uri=oe-17-8-6550

5. Pepeljugoski, P. K., Jeffrey, A., Taubenblatt, M., Offrein, B.J., Benner, A., et al., 2010, Low Power and High Density Optical Interconnects for Future Supercomputers, Optical Fiber Communication (OFC), Collocated National Fiber Optic Engineers Conference, 2010 Conference on (OFC/NFOEC), IEEE, pp 1-3.

http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=5465516&url=http%3A%2F%2Fieeexplore.ieee.org%2Fxpls%2Fabs_all.jsp%3Farnumber%3D5465516

6. NVM Express, Inc., 2016, NVM Express Specifications http://www.nvmexpress.org/specifications/

7. PCI SIG, 2017, Specifications. https://pcisig.com/specifications/pciexpress/

8. The Optical Society (OSA), 2016, OSA Industry Development Associates

http://www.osa.org/en-us/corporate_gateway/

9. The American Institute for Manufacturing Integrated Photonics (AIM Photonics), Homepage. http://www.aimphotonics.com/

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