Utilizing MIL-STD-1553B Digital Data Bus Devices Across an IEEE-1394A Serial Bus

Award Information
National Aeronautics and Space Administration
Award Year:
Phase I
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Small Business Information
Seakr Engineering, Inc
6221 S. Racine Circle, Centennial, CO, 80111
Hubzone Owned:
Minority Owned:
Woman Owned:
Principal Investigator:
Savio Chau
Group Supervisor
(818) 354-2845
Business Contact:
Joe Carroll
Program Manager
(303) 790-8499
Research Institution:
Jet Propulsion Laboratory
Robert S Cox
4800 Oak Grove Drive
Pasadena, CA, 91109
(818) 393-7107
Nonprofit college or university
The MIL-STD-1553B Bus is a widely supported data bus for avionics applications and compatible with most of the avionics equipment. However, its low data rate (1 Mbps) and command-response architecture are not suitable for many modern applications such as on-board autonomy. Therefore, the avionics industry recently has been interested in adopting the IEEE 1394A Bus as the next generation avionics bus. The IEEE 1394A Bus has a minimum bandwidth of 100 Mbps, which is two orders of magnitude faster than the 1553B Bus. In addition, its sophisticated protocol and multi-master capability can support distributed processing in advanced applications. One major obstacle in adopting the IEEE 1394A Bus is its compatibility with heritage equipment that is mostly compatible only with the 1553B Bus. It might take many years and large investments for the aerospace industry to convert all 1553B based equipment to the IEEE 1394A Bus.The objective of this task is to solidify the IEEE-1394A standard in spacecraft engineering by providing backward compatibility with MIL-STD-1553B. This backward compatibility allows heterogeneous communications between the IEEE-1394A and MIL-STD-1553B buses, so that both heritage and modern components can share a common bus architecture. Hence, this backward compatibility would shorten the time to acceptance of the IEEE 1394A Bus. In Phase I of this STTR, the functional requirements of the bridge and formats of the embedded commands have been defined. A software testbed has also been successfully implemented to demonstrate the read and write commands. In Phase II, a single board level implementation of the bridge will be designed, built and evaluated. This will provide the basis for further integration and miniaturization in a potential Phase III.

* information listed above is at the time of submission.

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