Next Generation Reconfigurable Field Programmable Gate Array

Award Information
Agency:
Department of Defense
Branch:
Air Force
Amount:
$99,757.00
Award Year:
2009
Program:
SBIR
Phase:
Phase I
Contract:
FA9453-09-M-0068
Agency Tracking Number:
F083-187-2379
Solicitation Year:
2008
Solicitation Topic Code:
AF083-187
Solicitation Number:
2008.3
Small Business Information
SEAKR Engineering, Incorporated
6221 South Racine Circle, Centennial, CO, 80111
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
122032006
Principal Investigator
 Ian Troxel
 CTO
 (303) 784-7673
 dcz@spacemicro.com
Business Contact
 Scott Anderson
Title: President
Phone: (303) 790-8499
Email: dstrobel@spacemicro.com
Research Institution
N/A
Abstract
As the US DOD and other agencies continue to undertake ever-challenging missions, the performance of space On-Board Processing (OBP) is often the limiting factor on what is achievable for a given mission objective.  To meet this demand, the defense industry as a whole has increasingly incorporated advanced technologies to bridge the performance gap brought on by increasing sensor data production, limited downlink capacity, and the need for real-time battlespace situational awareness.  The use of Field-Programmable Gate Arrays (FPGAs) have contributed significantly in increase performance, but drawbacks such as radiation susceptibility, power consumption, floating-point processing overhead, and a challenging programming model make them suboptimal solutions for many critical DoD aerospace missions.  Multi-core processing architectures show significant potential to address this performance gap.  MAESTRO is a 49-core processor under development by Boeing using Radiation-Hardened by Design (RHBD) techniques funded by the NRO On-board Processing Expandable Reconfigurable Architecture (OPERA) program.  The program is only funding for the development of the OPERA processor, and for Phase I, SEAKR proposes to lay the groundwork for developing a flexible MAESTRO space qualified On-Board Processing (OBP) system. BENEFIT: As the US DOD and other agencies continue to undertake ever-challenging missions, the performance of space On-Board Processing (OBP) is often the limiting factor on what is achievable for a given mission objective.  To meet this demand, the defense industry as a whole has increasingly incorporated advanced technologies to bridge the performance gap brought on by increasing sensor data production, limited downlink capacity, and the need for real-time battlespace situational awareness.  The use of Field-Programmable Gate Arrays (FPGAs) have contributed significantly in increase performance, but drawbacks such as radiation susceptibility, power consumption, floating-point processing overhead, and a challenging programming model make them suboptimal solutions for many critical DoD aerospace missions.  Multi-core processing architectures show significant potential to address this performance gap.  MAESTRO is a 49-core processor under development by Boeing using Radiation-Hardened by Design (RHBD) techniques funded by the NRO On-board Processing Expandable Reconfigurable Architecture (OPERA) program.  The program is only funding for the development of the OPERA processor, and for Phase I, SEAKR proposes to lay the groundwork for developing a flexible MAESTRO space qualified On-Board Processing (OBP) system.

* information listed above is at the time of submission.

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