Readout Integrated Circuit (IC) Technology for Strained Layer Superlattice Photodetectors

Award Information
Department of Defense
Air Force
Award Year:
Phase I
Award Id:
Agency Tracking Number:
Solicitation Year:
Solicitation Topic Code:
AF 09-160
Solicitation Number:
Small Business Information
100 Campus Drive, Marlborough, MA, 01752
Hubzone Owned:
Minority Owned:
Woman Owned:
Principal Investigator:
Gene Petilli
Director of Engineering
(585) 340-2352
Business Contact:
Timothy Brug
Director ADG Business Development
(508) 658-7686
Research Institution:
Intrinsix proposes a modular Read Out Integrated Circuit (ROIC) based on a uniquely architected overlapping serpentine read path that enables the use of high dynamic range sigma-delta modulator based analog-to-digital converters (ADC) for imaging applications. We have coined the project as "SnakeEye". The primary objective of this effort is to provide the specifications and architectural details for the design of a low cost ROIC optimized for use with Strained Layer Superlattice Photo-detectors for Un-Manned Air Vehicle(UAV) applications that increases the dynamic range of the ROIC 4 to 16 times, and enables rapid deployment of new sensor technology for UAV applications. SnakeEye's benefits are accomplished by leveraging several innovations: programmable SDM data converter design, overlapping serpentine ROIC read pattern, and fault-tolerant configuration of SDM-ADCs. BENEFIT: The three key benefits are: 1) High dynamic range enabled by Sigma-Delta Modulator (SDM) based serpentine read channel a. Fault & single event tolerance using redundant ADCs b. High SNR and reduced fixed pattern noise by digitally combined and compensated ADCs 2) Rapid lower cost deployment of new sensors while improving on SWaP of high end instruments. a. Utilizes industry standard, low power high-speed serial interfaces to simplify interchange of instruments b. Customized analog interface coupled to common signal acquisition block enables rapid deployment of new sensors, regardless of configuration or manufacturer 3) Performance of modern (sub 100nm CMOS) technology a. Column pitch down to 5um b. High throughput using multiple ADCs c. Enables integration of signal processing and information compression

* information listed above is at the time of submission.

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