FISO Digitizer for Flash Capture A/D Conversion

Numerous DoD systems critically rely on accurately capturing nanosecond transient signals. For sampling rates of 1 GS/s or greater, conventional flash A/D converters (ADCs) suffer from limited resolution (~8 bits), high power (ca. 5 watts/channel), and high cost. Extensive modeling conducted by Dakota Technologies, Inc. (DTI) and Lawrence Berkeley National Laboratory (LBNL) during Phase I proved that a fast-in slow-out (FISO) "flash capture" ADC architecture can provide an unprecedented combination of speed, resolution, power, and cost. The ability to independently optimize the sampling and conversion processes accounts for the breakthrough. In phase II, the DTI-LBNL team will design and fabricate a flash capture ADC based on this approach. This low-cost CMOS chip will capture 1024 analog samples on each of 4 channels at 1 to 10 GS/s, convert the samples into 10- or 12-bit digital values at a high rate, and dissipate less than 20 mW per channel. DTI will additionally conduct test bed demonstrations to validate the ADC's performance and advantages for biological agent detection and time-domain fluorescence. With these demonstrations, DTI will show that a FISO-based flash capture ADC yields superior solutions for applications ranging from compact, low-cost sensors to research-grade instruments.