Response to Advanced Solid State Memory Conversion with Advance On-board Test Capability

Award Information
Agency:
Department of Defense
Branch
Navy
Amount:
$79,736.00
Award Year:
2010
Program:
SBIR
Phase:
Phase I
Contract:
N68335-10-C-0527
Agency Tracking Number:
N102-129-0071
Solicitation Year:
2010
Solicitation Topic Code:
N102-129
Solicitation Number:
2010.2
Small Business Information
Digital Design Corporation
3820 Ventura Drive, Arlington Heights, IL, 60004
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
087725110
Principal Investigator:
Brian Donahoe
President
(847) 359-3828
brian@digidescorp.com
Business Contact:
Barb Maes
Manager
(847) 359-2242
barb@digidescorp.com
Research Institution:
n/a
Abstract
DDC will implement an innovative advanced Bandwidth Enhancement Block to raise sustained data write performance to over 500MB/s. This block adds to an existing architecture (already deployed by the military). The result will be very low SWAP as it is not necessary to run several drives to obtain the required speeds. Within the desired SWAP, the system can scale to well over 1GB/s write speeds, and can support drives in excess of 2TB. The current system will be restructured as an easily expandable rack and backplane solution. This includes an I/O slot that allows for card based support of a wide variety of sensor configurations. The FPGA design also allows for new memory densities to be "plug and play" - a new card can be inserted, without the need to pull the hardware or perform any programming. In that this system is "auto-sense", the inclusion of a front panel OLED will allow for simple and informative field system monitoring. The overall approach allows for rapid configuration of a wide variety of sensor combination, standards, and memory density required by the military. DDC is open to working with the customer for an optimal combination of features.

* information listed above is at the time of submission.

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