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Radiation Hardened High Speed Integrated Circuits Double Data Rate I/O for Extreme Operating Environments
Title: Design Scientist
Phone: (719) 531-0805
Title: Business Official
Phone: (719) 531-0805
Manned and robotic space missions require high-performance electronic control systems capable of operating for extended periods in harsh environments that are subject to radiation, extreme temperatures, vibration and shock. Semiconductor technologies capable of meeting these demanding requirements tend to have limited capabilities, are expensive, and are not easily configured for specific mission requirements. Leading-edge applications will benefit from the ability to implement high speed interconnect protocols between host processors and system slaves, such as sensors, actuators, power managers, imagers and transceivers. The development of a Radiation Hardened Double Data Rate (DDR) embedded macro is proposed for insertion into digital integrated circuits (ICs) suitable for scalable single and multi-core processors, special purpose logic functions and scalable memory blocks on a space-qualified, radiation hardened integrated circuit digital fabric. A NASA-funded Structured ASIC architecture is under development at Micro-RDC, capable of meeting space-grade requirements while creating a cost-effective, quick-turn development environment. The SASIC fabric will implement known Radiation-Hardened-By-Design (RHBD) techniques on an advanced 32nm Silicon on Insulator (SOI) CMOS process, supporting high-density, high-speed low-power implementations. A unique Master Tile architecture with through-seal-ring connections allows the designer to define dedicated logic functions, scalable memory blocks and user-defined I/Os; all on a single, scalable integrated circuit. The 32nm SOI CMOS process technology platform incorporates RHBD building-blocks (e.g. flip-flops, gates, distributed memory, block memory, I/O) required for the systems designer to implement functional blocks for application-specific requirements. During this project, key blocks for a DDR3 macro will be specified and evaluated for optimum inclusion into the Micro-RDC SASIC.
* Information listed above is at the time of submission. *