SBIR Phase I:EPITAXY-LEVEL PACKAGING

Award Information
Agency:
National Science Foundation
Branch
n/a
Amount:
$150,000.00
Award Year:
2010
Program:
SBIR
Phase:
Phase I
Contract:
1013913
Award Id:
99099
Agency Tracking Number:
1013913
Solicitation Year:
n/a
Solicitation Topic Code:
IC4
Solicitation Number:
n/a
Small Business Information
40660 Las Palmas Ave, Fremont, CA, 94539
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
179041855
Principal Investigator:
Eric Pan
PhD
(510) 252-0878
eric_pan@meridiandeployment.com
Business Contact:
Eric Pan
PhD
(510) 252-0878
eric_pan@meridiandeployment.com
Research Institution:
n/a
Abstract
This Small Business Innovation Research (SBIR) Phase I project investigates a novel epitaxial process that simultaneously grows and transfers epitaxial structures from a semiconductor substrate to an assembly substrate. It addresses a number of fundamental barriers persist to mass production and commercialization of compound semiconductor devices namely: 1)material cost, 2) substrate size, 3) component/subsystem integration, and 4) thermal issue. Among the cost drivers, the crystalline substrate and epitaxial layer typically account for more than half of the finished wafer cost. Depending on the type of materials for each application, wafer sizes vary widely. The resulting barrier is a lack of a technology platform (fabrication and integration platforms either monolithic or modular) versatile enough to intermix and integrate devices made from different materials that allow higher performance and/or functionality. In most high performance devices, there is a need for lower the thermal resistance between device?s active layer and heat sink. The project goals are to demonstrate feasibility for manufacturing by demonstrating clear advantages over conventional methods in providing low cost, high quality, and low thermal resistance epitaxial materials. Unlike prior art layer transfer techniques, this method provides high yield and streamlines package and assembly steps by eliminating some processing steps. The broader impact/commercial potential of this project will be to enable wide applications, especially in defense, space, and commercial sectors. Using our innovative method, the contact area of epitaxial layer to crystalline substrate is reduced and epitaxial growth volume (both vertical and lateral overgrowth) is defined by a patterned assembly substrate. The reduced contact area enables a highyield layer transfer process. The assembly substrate standardizes substrate size for further processing regardless of the original material sizes. The epitaxial layer transferred directly onto an assembly substrate provides a unit building block for higher level of device and subsystem integration. These applications and devices include but not limited to optoelectronics such as lasers, sensors, optical data storage, fiber optics, light emitting diodes (LED), and photovoltaics (PV), radio frequency (RF) and wireless systems, and microwave, millimeterwave, radar, and satellite communication systems. For commercialization of our solution, our target customers are manufacturers of photonic components that require highyield layer transfer, fast heat transfer at semiconductor device level, and integrability of different materials for high performance. The addressable market in manufacturing of photonic and communication components is estimated to be over $30 billion.

* information listed above is at the time of submission.

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