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High Reliability SiC Power Switch Module Packaging

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: FA8650-07-M-2714
Agency Tracking Number: O063-EP7-1090
Amount: $99,376.00
Phase: Phase I
Program: SBIR
Solicitation Topic Code: OSD06-EP7
Solicitation Number: 2006.3
Solicitation Year: 2006
Award Year: 2007
Award Start Date (Proposal Award Date): 2007-02-16
Award End Date (Contract End Date): 2008-02-16
Small Business Information
Denal Way - m/s 408
Vestal, NY 13850
United States
DUNS: 128899148
HUBZone Owned: No
Woman Owned: No
Socially and Economically Disadvantaged: No
Principal Investigator
 Douglas C Hopkins
 (607) 729-9949
Business Contact
 Douglas Hopkins
Title: President
Phone: (607) 729-9949
Email: D.Hopkins@IEEE.Org
Research Institution

Silicon Carbide (SiC) power semiconductor devices inherently operate at higher frequencies and temperatures than silicon counterparts, allowing design of denser power electronic systems. To take full advantage in early stages of device maturation, related packaging must be developed that provides reliable paralleling of many die and manages large thermal gradients during wide-temperature-range cycling. The goal is to demonstrate high current (<1000A), high voltage (<1,800V) module packaging of devices for operation in –40C to 250C ambient with operation >500kHz. DCHopkins & Associates is a technology developer of power electronic systems from electrical concepts to physical design with emphasis on reliability. During Phase-I, DCH&A will demonstrate through modeling and selective testing, two packaging approaches. The packaging encompasses material selection, structural definition and processing. The design is driven first by reliability needs, then electrical performance. For highly reliable wide-temperature operation, physical module components must be selected to manage inherent stresses caused by CTE differences. Stresses are managed by optimum selection of material type, thicknesses and stiffness (modulus of elasticity), and thermal conductance (to reduce thermal gradients). Electrical performance is meet by optimum selection of electrical layout to minimize inductance and resistance, and, consequently, decrease thermal gradients that exacerbate stress gradients.

* Information listed above is at the time of submission. *

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