DESIGN OF A HIGH-SPEED INTELLIGENT BUFFER/MEMORY FOR THE FASTBUS

Award Information
Agency:
Department of Energy
Branch:
N/A
Amount:
$499,585.00
Award Year:
1985
Program:
SBIR
Phase:
Phase II
Contract:
N/A
Agency Tracking Number:
1202
Solicitation Year:
N/A
Solicitation Topic Code:
N/A
Solicitation Number:
N/A
Small Business Information
Digital Video Processing Inc.
2401 Research Blvd, Rockville, MD, 20850
Hubzone Owned:
N
Socially and Economically Disadvantaged:
N
Woman Owned:
N
Duns:
N/A
Principal Investigator
 Matthew W. Price
 Senior Design Engineer
 () -
Business Contact
Phone: () -
Research Institution
N/A
Abstract
THERE IS A CURRENT NEED FOR A STANDARD INTERFACE BETWEEN MODERN, HIGH SPEED COMPUTERS AND DATA ACQUISITION SYSTEMS. A NEW INSTRUMENTATION STANDARD, THE FASTBUS, DESIGNED SPECIFICALLY TO MEET THE INTERFACE NEED BETWEEN PHYSICS EXPERIMENTS AND MODERN COMPUTERS IS CURRENTLY UNDERGOING PROTOTYPE TESTING. UNFORTUNATELY, DUE TO THE LIMITED NUMBER OF APPLICATIONS OF THE FASTBUS TO SPECIFIC INDUSTRY AND GOVERNMENT PROJECTS, RESEARCH IS NEEDED FOR THE DEVELOPMENT AND DESIGN SPECIFICATIONS OF FASTBUS MODULES. OF PRIMARY CONCERN TO FASTBUS DATA ACQUISITION SYSTEMS IS AN INTELLIGENT FAST BUFFER. DVP, INC. PROPOSES TO DETERMINE THE FEASIBILITY OF DEVELOPING A LOW-POWER, LOW-COST, EXTREMELY FAST, HIGHLY DEPENDABLE, INTELLIGENT BUFFER. THE PROPOSED DESIGN APPROACH IS UNIQUE IN THAT BIT-SLICE PROCESSOR CONTROLLED MOS VLSI ICS ARE USED TO PROVIDE DYNAMIC ACCESS TIMES RIVALING ECL MEMORIES. THE FAST ACCESS TIMES ARE FACILITATED BY EMPLOYING STATE-OF-THE ART VIDEO FRAME STORE BUFFER TECHNIQUES. THE FINAL MODULE WILL BE CAPABLE OF FULL BANDWIDTH REAL-TIME OPERATION IN A FASTBUS ENVIRONMENT. THE MODULE WILL BE CONFIGURABLE AS A LARGE CAPACITY, HIGHLY FLEXIBLE, GENERAL PURPOSE MEMORY, OR AS A SPECIALIZED HIGH SPEED FIFO BUFFER FOR DATA ACQUISITION.

* information listed above is at the time of submission.

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