THE FASTBUS

Award Information
Agency: Department of Energy
Branch: N/A
Contract: N/A
Agency Tracking Number: 2498
Amount: $49,586.00
Phase: Phase I
Program: SBIR
Awards Year: 1985
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
7841 Epsilon Drive, Rockville, MD, 20855
DUNS: N/A
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 MR. MATTHEW W. PRICE
 PRINCIPAL INVESTIGATOR
 (301) 670-9282
Business Contact
Phone: () -
Research Institution
N/A
Abstract
THE FASTBUS (IEEE STANDARD 960) IS A NEW 32-BIT BUS STANDARD DEVELOPED FOR DOE FOR USE IN HIGH-SPEED DATA ACQUISITION AND MULTIPROCESSING ENVIRONMENTS, AND IT IS ONLY NOW BEGINNING TO APPEAR IN MANUFACTURES CATALOGS. PROTOTYPE SYSTEMS ARE CURRENTLY IN OPERATION AND LARGE SSYTEMS ARE BEING BUILT, BUT THERE ARE. AS OF NOW, NO SOURCES OD FASTBUS INTERFACE CHIPS. HTESE ARE INTEGRATED CIRCUITS (ICS), WHICH ALLOW A BOARD DESIGNER TO EASILY ADAPT A PARTICULAR DESIGN TO THE FASTBUS ENVIRONMENT. THE FASTBUS IS UNIQUE IN ITS LACK OF SUPPORT FROM SEMICONDUCTOR COMPANIES AS ALL OTHER MAJOR 32-BIT BUS STANDARDS ARE BEING SUPPORTED BY ONE OR MORE IC MANUFACTURERS. THIS STUDY AIMS AT FILLING THIS GAP. SEVERAL EMITTER COUPLED LOGIC (ECL) GATE ARRAYS SUITABLE FOR INTERFACING CIRCUITRY TO THE FASTBUS WILL BE DESIGNED AND IMPLEMENTED. THESE ICS WILL ALLOW FASTBUS DESIGNERS AND MANUFACTURERS EASILY TO ADAPT THEIR IDEAS TO THE FASTBUS ENVIRONMENT, WITHOUT THE NEED FOR AN EXTENSIVE INTERFACE DESIGN AND ITS ASSOCIATED DEBUGGING EFFORT.

* Information listed above is at the time of submission. *

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