Monolithic, InGaAs-on-Silicon, Optical Interconnects for Massively Parallel Computing

Award Information
Agency: Department of Defense
Branch: Air Force
Contract: N/A
Agency Tracking Number: 27982
Amount: $735,012.00
Phase: Phase II
Program: SBIR
Awards Year: 1996
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
186 Princeton-hightstown Rd., Bldg. 3a, Box 1, Cranbury, NJ, 08512
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Abhay M. Joshi
 (609) 275-0011
Business Contact
Phone: () -
Research Institution
A solution to the problem of interchip interconnects is proposed that employs electro-optical links implemented monolithically on silicon substrates. This approach addresses the fundamental material incompatibility problem of opto-electronics by implementing electronics in silicon and optical components using III-V compounds on a single chip. This is made possible through the use of "selective epitaxy", a technique that Discovery Semi- conductors has developed to grow device grade InGaAs-on-silicon substrates. Growth of InGaAs crystals on a lattice mismatched substrate is improved by limiting the growth area, selecting appropriately oriented wafers, and controlling the growth conditions. Dr. Eugene Fitzgerald of M.I.T., who pioneered selective epitaxy, will consult. This capability will be used to grow dual function, infrared In0.53Ga0.47As p-i-n photodiode/light emitting diode structures operating at 1100 to 1600 nm on a silicon CMOS circuit. These devices can be used to form optical links between separate seminconductor chips. A simple, proximity focussed architecture is presented where multiple silicon chips are stacked together. The optical emitter/detector pairs then form the links between the layers of the stack. A device that has all the components required to implement this scheme is proposed for the Phase I work. A more elaborate multi-plane, optically coupled, massively parallel processor is anticipated for development in Phase II.

* Information listed above is at the time of submission. *

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