TECHNOLOGY AREA(S): Sensors, Electronics
OBJECTIVE: To develop a high performance carbon nanotube (CNT) based millimeter-wave transistor technology and demonstrate monolithic millimeter-wave integrated circuits (MMICs) based on this technology with improved power efficiency, linearity, noise and dynamic range performance over existing GaAs, SiGe and RF-CMOS technologies.
DESCRIPTION: Semiconducting single-walled carbon nanotubes (CNTs) have very desirable characteristics which are ideal for field-effect transistor (FET) channels, such as one-dimensional (1D) ballistic transport, high carrier mobility, inherent linearity and small size. Single-CNT FETs with room-temperature ballistic transport approaching the quantum conductance limit of 2Go=4e2/h=155uS was demonstrated more than a decade ago. It was predicted, based on extrapolation from individual CNT characteristics that FETs consisting of parallel arrays of CNTs will lead to significant improvement in energy-delay product and therefore speed and power consumption for logic devices, and enhanced linearity and efficiency for RF applications. Such an enabling technology will have a major impact in reducing size, weight, power and cost (SWAP-C) of electronic components. However, these potentials were not fully realized due to a number of technical challenges: 1) the lack of techniques to eliminate tube-tube cross junctions and achieve parallel aligned CNT arrays with optimal packing density of CNTs; 2) the presence of metallic CNTs leading to less than ideal semiconducting purity; 3) difficulty of creating highly conductive ohmic contact to the CNT arrays. A number of recent developments in the past few years have made significant progress in toward overcoming these challenges in sorting, processing, alignment and contacts of CNT arrays, and led to CNT FETs that could outperform conventional Si and GaAs FETs. For the first time, aligned parallel CNT arrays with higher than 99.98% semiconducting purity were realized on Silicon and quartz substrate. FETs built using these CNT arrays have realized room-temperature quasi-ballistic transport with channel conductance approaching the quantum conductance limit and 7 times higher than previous state-of-the-art CNT array FETs. Furthermore, high frequency FETs using well aligned CNT arrays deposited on quartz substrates have achieved current-gain cutoff frequency (ft) and maximum oscillation frequency (fmax) greater than 70 GHz. These breakthroughs in device performance offer the opportunity to finally utilize one-dimensional (1D) transport properties of thousands of aligned, gate-controllable conduction pathways possessing linear current density characteristics for improving high-frequency circuit performance. These newly demonstrated CNT FETs should show excellent performance at the microwave frequencies. However, in order to fully realize the potential of CNT FETs for millimeter-wave frequencies and higher, continued research within academic community is needed in order to achieve even higher ft and fmax, likely much greater than 100GHz, by further improvements in array purity, alignment and contact resistance. New approaches are also needed to realize large well-aligned, high-purity CNT arrays at the wafer-scale level for creating monolithic integrated circuits beyond individual devices. The goal of this topic is to leverage these developments toward creating a high performance CNT-based transistor technology and wafer-scale monolithic integrated circuits at millimeter-wave frequencies that can be commercialized to outperform incumbent semiconductor high frequency technologies (GaAs, SiGe, RF-CMOS) yet at much lower cost.
PHASE I: Establish a robust process capable of producing high performance RF transistors based on CNTs. The process must be scalable to wafer size to enable fabrication of monolithic integrated circuits. Develop new pathways and process flow innovations in CNT alignment & deposition, material contact and doping to create high quality CNT arrays beyond current state-of-the-art for device engineering. In particular, prototype CNT RF transistors with the following metrics must be demonstrated in Phase I. DC: ION/W >500 ìA/ìm, ION/IOFF > 1000; RF: fT and fmax > 50GHz, and a third-order intercept (IP3) at least 10dB higher than its 1dB compression power (P1dB).
PHASE II: Demonstrate functional millimeter-wave monolithic integrated circuits that exceed GaAs, SiGe, RF-CMOS in DC and RF metrics based on the process developed in Phase I. Develop a hysteresis-free CMOS compatible process flow which can be integrated into an existing commercial CMOS process. Demonstrate improved device performance with the following metrics. DC: ION/W >700 ìA/ìm, gm/W > 700mS/mm; RF: fT > 130GHz, fmax > 180GHz, and a third-order intercept (IP3) at least 15dB higher than its 1dB compression power (P1dB). Functional circuits to be demonstrated should include a low noise amplifier with noise figure less than 2 dB and a power amplifier with output power greater than 30 dBm, both operating at 30 GHz.
PHASE III: To qualify the process with a trusted foundry in order to de-risk technology for monolithic heterogeneous integration with CMOS. Undertake reliability testing and radiation qualification. Produce a process design kit (PDK). Commercialize the technology via a trusted foundry for technology availability to the defense and military markets. CNT-based MMICs will have a variety of applications in the military, defense, aerospace and ultimately the consumer electronic markets.
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KEYWORDS: Carbon Nanotubes, Field-effect Transistors, Millimeter-wave, Microwave Monolithic Integrated Circuits (MMICs)