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Adiabatic/Reversible Logic Test Chip

Description:

TECHNOLOGY AREA(S): Space Platforms 

OBJECTIVE: The goal of this STTR topic is to develop and characterize a test chip implementing adiabatic/reversible logic side-by-side with conventional logic to ascertain the potential applicability of adiabatic/reversible logic to space processing. 

DESCRIPTION: The processing requirements for many space-based missions, such as ISR and SSA, are expected to grow dramatically in the next few decades, requiring much more processing be done in the highly energy-constrained space environment. This STTR topic will investigate the ability of adiabatic/reversible logic circuit design techniques to reduce the power requirements of future high performance space microprocessors and enable the efficient utilization of state-of-the-art processor technologies in space. This technology offers the promise of greatly reduced energy costs by recycling the energy used in logical operations at the device level, at the cost of lower operating speeds. This topic seeks to understand the power/speed tradeoffs of these techniques by implementing them in an adiabatic test chip. Currently, embedded versions of processor technologies sacrifice speed and memory capacity to save power by reducing clock frequency and voltage. For example, NVidia’s Tesla P100 GPU (Pascal architecture) is capable of delivering 4.7/9.3 TFLOPS of double/single precision performance, but require 250W of power.[1] It’s low power embedded GPU cousin, the NVidia TX2, delivers 1 TFLOP single precision arithmetic with 7.5 W.[1] Adiabatic logic variants such as two-level adiabatic logic (2LAL), split-level charge recovery logic (SCRL), and reversible energy recovery logic (RERL) have been shown to have some potential to reduce energy dissipation by factors of 10 or more depending on the speed at which the logic is run.[2]-[3] At least one university group is building a reduced instruction set processor using adiabatic techniques.[4] For this effort, a non-rad hard test chip implementing representative functional blocks used in logic and memory circuits such as adders, shift registers, etc. will be designed using a range of conventional and adiabatic design techniques and implemented in a CMOS process for which rad-hard by design (RHBD) support exists. The proposed test chip and studies will enable the Air Force to determine whether adiabatic techniques can be combined with the highest performing commercial processor technologies to enable ultra-low power, high performance, digital processing for space. 

PHASE I: The vendor will design a chip implementing representative test blocks of logic and memory devices in the best adiabatic circuit design techniques available. The chip should be built on 90 or 32 nm technology and operate at speeds in the range from 0.5-1.5 GHz. SPICE models describing the expected behavior of the chip will be developed and provided to the government. 

PHASE II: The vendor will implement the design developed in Phase I in a standard CMOS process, experimentally characterize the power utilization of each test device and adiabatic design technique combination and compare the experimental power utilization with that predicted using the developed SPICE models. Test chips will be supplied to the government for independent testing. 

PHASE III: The vendor will apply the lessons learned to the design of larger prototype circuits or low power microprocessor. 

REFERENCES: 

1: Tesla P100 and Jetson TX2 product descriptions at www.nvidia.com.

2:  Mehrdad Khatir, Alireza Ejlali, Amir Moradi, "Improving the energy efficiency of reversible logic circuits by the combined use of adiabatic styles", INTEGRATION, the VLSI journal 44, pp. 12–21 (2011).

3:  Venkiteswaran Anantharam, Maojiao He, Krishna Natarajan, Huikai Xie, and Michael P. Frank, "Driving Fully-Adiabatic Logic Circuits Using Custom High-Q MEMS Resonators." in ESA/VLSI, pp. 5-11, (2004).

4:  C. O. Campos-Aguillón, R. Celis-Cordova, I. K. Hänninen, C. S. Lent, A. O. Orlov and G. L. Snider, "A mini-MIPS microprocessor for adiabatic computing", 2016 IEEE International Conference on Rebooting Computing (ICRC), pp. 1-7, (2016).

KEYWORDS: Adiabatic Circuits, Reversible Circuits 

CONTACT(S): 

Andrew C. Pineda (AFRL/RVSW) 

(505) 853-2509 

andrew.pineda.6@us.af.mil 

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