Micro-Architecture Development Tools for Embedded Processing

Award Information
Agency: Department of Defense
Branch: Defense Advanced Research Projects Agency
Contract: DAAH0101CR121
Agency Tracking Number: 01SB1-0079
Amount: $98,918.00
Phase: Phase I
Program: SBIR
Awards Year: 2001
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
EDAPTIVE COMPUTING, INC.
2161 Blanton Dr, Dayton, OH, 45342
DUNS: 031764616
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 Jeffrey Walrath
 Principal Researcher
 (937) 433-0477
 j.walrath@edaptive.com
Business Contact
 Dale Kirby
Title: Vice President
Phone: (937) 433-0477
Email: d.kirby@edaptive.com
Research Institution
N/A
Abstract
EDAptive Computing, Inc. (EDAptive) and Dr. Ranga Vemuri of the University of Cincinnati present a unique and commercially viable solution to the problem of design space exploration, tradeoff analysis, and performance evaluation of embedded, system-levelmalleable micro-architectures. Our Embedded Micro Architecture SWEPT Simulator and Integrated Design Space Exploration and Tradeoff ANalysis Tool (ASSISTANT) program will apply previous research work in performance modeling and evaluation techniquesutilizing attributed nodes-only graph grammars to the problem of parameterization, manipulation, and simulation of various design space constraints. Specifically, we propose ASSISTANT with the following capabilities: 1) aid design engineers in thedevelopment, debug, verification, and generation of parameterized, executable design models automatically configurable at run-time for various embedded, system-level micro-architectures; 2) provide an easy-to-use shell interface for hardware applicationengineers to enter parameter data, configure, simulate, and debug the executable models for design space exploration and tradeoff analysis; 3) provide a procedural interface for the invocation of the executable models from third party tools. To accomplishthis task, we will utilize Dr. Vemuri's research work in a performance description language suited for such design and modeling scenarios called PDL+.The technology developed under this SBIR applies to both military and commercial sectors and can be usedin design and development environments for application and design engineering targeting system-level embedded, heterogeneous, and malleable computing hardware.

* information listed above is at the time of submission.

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