VLSI DESIGNS

Award Information
Agency: Department of Defense
Branch: Navy
Contract: N/A
Agency Tracking Number: 3859
Amount: $49,999.00
Phase: Phase I
Program: SBIR
Awards Year: 1986
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
Edwards Communications Electro
335 Park St Ne, Vienna, VA, 22180
DUNS: N/A
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 RAJ B EDWARDS
 (703) 938-5138
Business Contact
Phone: () -
Research Institution
N/A
Abstract
THE COMPLEXITY OF VLSI CIRCUITS MAKES THE PROCESS OF DEVELOPING TESTS A VERY COMPLEX AND COSTLY TASK. HOWEVER, NUMEROUS DESIGN FOR TESTABILITY TECHNIQUES EXIST AND ARE KNOWN TO EXPERTS IN THE FIELD. THIS PROPOSAL DEALS WITH ASPECTS OF THE DESIGN OF AN EXPERT CAD SYSTEM TO AID A DESIGNER IN CREATING A TESTABLE CHIP, AND ALSO IN CREATING THE TEST PROGRAM ITSELF. THE WORK WILL EXTEND RESEARCH WE HAVE ALREADY CARRIED OUT ON THIS PROBLEM. THE PROPOSED SYSTEM IS CAPABLE OF MODELING EXISTING TEST TECHNIQUES AS A.I. FRAMES, AND OF AUTOMATICALLY EMBEDDING THESE TECHNIQUES INTO A CHIP BEING DESIGNED. NEW TEST TECHNIQUES, AS THEY ARE INVENTED BY TEST EXPERTS, CAN BE EASILY ADDED TO THE SYSTEM BY TEST EXPERTS. THE PROPOSED WORK DEALS WITH 4 KEY TASKS: (1) DEFINING A SYSTEM ARCHITECTURE FOR SUCH AN EXPERT SYSTEM, (2) DETERMINIG A SET OF BIT STRUCTURES AND THEIR CHARACTERISTICS USEFUL FOR GATE ARRAY CIRCUITS; (3) DETERMINING WAYS TO CALCULATE VALUES FOR MEASURES FOR TEST TECHNIQUES SO THAT AN INTELLIGENT SELECTION BETWEEN TECHNIQUES CAN BE MADE; AND (4) DEVELOPING WAYS TO PARTITION A CIRCUIT SO THAT EACH PARTITION CAN BE MADE TESTABLE.

* information listed above is at the time of submission.

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