AN INNOVATIVE APPROACH TO PRODUCE MULTI-MEGARAD HARD ELECTRONIC DEVICES FOR SPACEBORNE APPLICATIONS HAS BEEN PROPOSED, WHEREBY JUNCTION FIELD EFFECT TRANSISTORS (JFET) ARE DEVELOPED USING SILICON-ONINSULATOR (SOI) TECHNOLOGY.

Award Information
Agency: Department of Defense
Branch: Defense Threat Reduction Agency
Contract: N/A
Agency Tracking Number: 3872
Amount: $57,998.00
Phase: Phase I
Program: SBIR
Awards Year: 1986
Solicitation Year: N/A
Solicitation Topic Code: N/A
Solicitation Number: N/A
Small Business Information
23887 Madison St, Torrance, CA, 90505
DUNS: N/A
HUBZone Owned: N
Woman Owned: N
Socially and Economically Disadvantaged: N
Principal Investigator
 MICHAEL LEE
 (213) 373-8779
Business Contact
Phone: () -
Research Institution
N/A
Abstract
AN INNOVATIVE APPROACH TO PRODUCE MULTI-MEGARAD HARD ELECTRONIC DEVICES FOR SPACEBORNE APPLICATIONS HAS BEEN PROPOSED, WHEREBY JUNCTION FIELD EFFECT TRANSISTORS (JFET) ARE DEVELOPED USING SILICON-ONINSULATOR (SOI) TECHNOLOGY. THE MULTIMEGARAD HARDNESS IS DERIVED FROM THE 'BURIED' CHANNEL OF THE JFET DEVICES AND THE REDUCTION OF ELECTROMIGRATION OF TRAPPED AND INDUCED CHARGES OF THE WELL-MATCHED SILICON/OXIDE INTERFACE OF THE SILICON-ON-INSULATOR WAFER, FABRICATED BY OXYGEN IMPLANT OF SILICON WAFER. THIS PROPOSED EFFORT IS PHASE 1 OF A 3-PHASE PROGRAM, CONCEIVED SPECIFICALLY TO EXPLOIT THE EMERGING SOI TECHNOLOGY BASED ON THE SILICON-IMPLANT-OXIDE (SIMOX) PROCESS. THE MAJOR TASKS FOR PHASE I ARE: ANALYSIS AND MODELING OF COMPLEMENTARY JFET (CJFET) DEVICES AND CIRCUITS.

* Information listed above is at the time of submission. *

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