Enhancing FPGA Performance Through Integrated Optical Interconnects

Award Information
Agency:
Department of Defense
Branch
Air Force
Amount:
$749,997.00
Award Year:
2008
Program:
STTR
Phase:
Phase II
Contract:
FA9550-08-C-0019
Award Id:
78115
Agency Tracking Number:
F064-006-0416
Solicitation Year:
n/a
Solicitation Topic Code:
n/a
Solicitation Number:
n/a
Small Business Information
51 East Main Street, Suite 203, Newark, DE, 19711
Hubzone Owned:
N
Minority Owned:
N
Woman Owned:
N
Duns:
071744143
Principal Investigator:
Ahmed Sharkawy
Director Of Photonic Applications
(302) 456-9003
sharkawy@emphotonics.com
Business Contact:
Eric Kelmelis
CEO
(302) 456-9003
kelmelis@emphotonics.com
Research Institute:
UNIV. OF DELAWARE
Dennis Prather
140 Evans Hall
Newark, DE, 19716
(302) 831-8170
Nonprofit college or university
Abstract
FPGAs have attracted a great deal of attention over the past decade because of their performance, scalability, and cost relative to traditional hardware platforms. However, one of the most significant disadvantages of FPGAs is based on the underlying architecture on which they are built. Specifically, routing delay through the chip is one of the largest bottlenecks in developing FPGA-based applications. Routing delay typically accounts for at least 50% of the overall system delay and can easily account for 80-95% of the delay. In fact, as processes are refined and feature sizes shrink, routing delay is expected to increase as logic gates will become faster and will be forced to wait for data inputs to arrive. Thus, there is a clear need for a radically new FPGA architecture that minimizes the routing delay through the chip to enable increased performance, reduced costs, and faster time to market. To this end, we propose the development of an optically switched FPGA. By removing the electrical interconnections between logic blocks, data can be quickly and efficiently routed across the FPGA. Such a novel design will eliminate the routing bottleneck associated with existing FPGA architectures and enable the rapid development of high performance FPGA systems.

* information listed above is at the time of submission.

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